參數(shù)資料
型號(hào): R8820LV
廠商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT RISC MICROCONTROLLER
中文描述: 16位RISC微控制器
文件頁(yè)數(shù): 70/98頁(yè)
文件大?。?/td> 1000K
代理商: R8820LV
R DC
17. Asynchronous Serial Port
R8820LV has two asynchronous serial ports, which provide the TXD, RXD pins for the full duplex bi-directional data transfer
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
70
and with handshaking signals CTS, ENRX, RTS,
RTR
. The serial ports support : 9-bit, 8-bit or 7-bit data transfer; odd
parity, even parity, or no parity; 1 stop bits; Error detection; DMA transfers through the serial port; Multi-drop protocol (9-bit)
support; Double buffers for transmit and receive.
The receive/transmit clock is based on the microprocessor clock. The serial port can be used in power-saved mode, but the
transfer rate must be adjusted to correctly reflect the new internal operating frequency. Software is programmed through the
registers ,(80h, 82h, 84h, 86h, 88h – for port 0), ( 10h,12h,14h,16h,18h – for port 1) to configure the asynchronous serial port.
17.1 Serial Port Flow Control
The two serial ports provided with two data pins (RXD and TXD) and two flow control signals (RTS,
RTR
). Hardware flow
control is enabled when the FC bit in the Serial Port control Register is set. And the flow control signals are configured by
software to support several different protocols.
17.1.1 DCE/DTE Protocol
The R8820LV can be as a DCE (Data Communication Equipment) or as a DTE ( Data Terminal Equipment). This protocol
provides flow control where one serial port is receiving data and other serial port is sending data. To implement the DCE
device, the ENRX bit should be set and the RTS bit should be cleared for the associated serial port. To implement the DTE
device, the ENRX bit should be cleared and the RTS bit should be set for the associated serial port. The ENRX bit and RTS
bit are in the register F2h.
The DCE/DTE protocol is asymmetric interface since the DTE device can not signal the DCE device that is ready to receive
Transmit
Data Register(84h),(14h)
Transmit
Hold Register
Transmit
Shift Regoster
Receive
Data Register(86h),(16h)
Receive
Buffer
Receive Shift
Register
TXD
Control
Logic
Control Register(80h),(10h)
Status Register(82h),(12h)
Baud Rate
Divisor Register(88h),(18h)
Interrupt Request
RXD
Internal Address/Data Bus
Serial Port Block Diagram
16 bit
8 bit
8 bit
16 bit
16 bit
8 bit
8 bit
RTS
ENRX
RTR
CTS
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