參數(shù)資料
型號(hào)： R8820LV
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT RISC MICROCONTROLLER
中文描述： 16位RISC微控制器
文件頁(yè)數(shù)： 33/98頁(yè)
文件大?。?/td> 1000K
代理商： R8820LV
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
33
Set 0: external ready is required.
Bit 1-0 : R1-R0
, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the LCSmemory area.
(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state
(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state
12.3
MCSx
The memory block of MCS4-MCS0can be located anywhere within the 1M bytes memory space, exclusive of the
areas associated with theUCSand LCSchip selects. The maximum MCSx active memory range is 512k bytes.
The MCSx chip selects are programmed through two registers A6h and A8h, and these select pins are not active on reset.
Both A6h and A8h registers must be accessed with a read or write to activate MCS4-MCS0. There aren’t default value on
A6h and A8h registers, so the A6h and A8h must be programmed first before MCS4-MCS0active.
Bit 15-7 : BA19-BA13
, Base Address. The BA19-BA13 correspond to bits 19-13 of the 1M bytes (20-bits) programmable
base address of the MCSchip select block. The bits 12 to 0 of the base address are always 0.
The base address can be set to any integer multiple of the size of the memory block size selected in these bits. For
example, if the midrange block is 32Kbytes, only the bits BA19 to BA15 can be programmed. So the block address
could be locate at 20000h or 38000h but not in 22000h.
The base address of the MCSchip select can be set to 00000h only if the LCSchip select is not active. And the
MCSchip select address range is not allowed to overlap the LCS chip select address range.
TheMCSchip select address range also is not allowed to overlap theUCSchip select address range.
Bit 8-3
: Reserved
Bit 2: R2
, Ready Mode. This bit is configured to enable/disable the wait states inserted for theMCSchip selects. The R1,R0
bits of this register determine the number of wait state to insert.
set to 1: external ready is ignored
set to 0: external ready is required
Bit 1-0 : R1-R0
, Wait-State value. The R1,R0 determines the number of wait states inserted into aMCSaccess.
(R1,R0) : (1,1) – 3 wait states , (1,0) – 2 wait states, (0,1) – 1 wait states , (0,0) – 0 wait states
Midranage Memory Chip Select Register
Offset : A6h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
BA19 - BA13
1
1
1
1
R2
R1
R0
1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
R8821 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER
R8822 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER
R8822I 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER
R8830 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER
R8830I 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER
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