參數(shù)資料
型號(hào): R8820LV
廠商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT RISC MICROCONTROLLER
中文描述: 16位RISC微控制器
文件頁數(shù): 64/98頁
文件大小: 1000K
代理商: R8820LV
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
64
Set 0: The Maxcount Compare A register of timer 1 is being used
Bit 11-6
: Reserved.
Bit 5: MC
, Maximum Count Bit. When the timer reaches its maximum count, the MC bit will set to 1 by H/W. In dual
maxcount mode, this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached. This
bit is set regardless of the EN bit (66h.15).
Bit 4: RTG
, Re-trigger Bit. This bit define the control function by the input signal of TMRIN1 pin. When EXT=1 (5Eh.2),
this bit is ignored.
Set 1: Timer1 Count Register (58h) counts internal events; Reset the counting on every TMRIN1 input signal from low
go high (rising edge trigger).
Set 0: Low input holds the timer 1 Count Register (58h) value; High input enables the counting which counts internal
events.
The definition of setting the (EXT , RTG )
( 0 , 0 ) – Timer1 counts the internal events. if the TMRIN1 pin remains high.
( 0 , 1 ) -- Timer1 counts the internal events; count register reset on every rising transition on the TMRIN1 pin
( 1 , x ) -- TMRIN1 pin input acts as clock source and timer1 count register increase one every four external clock.
Bit 3: P
, Prescaler Bit. This bit and EXT(5Eh.2) define the timer 1 clock source.
The definition of setting the (EXT , P )
( 0 , 0 ) – Timer1 Count Register increase one every four internal processor clock.
( 0 , 1 ) – Timer1 count register increase one which prescal by timer 2.
( 1 , x ) -- TMRIN1 pin input acts as clock source and Timer1 Count Register increase one every four external clock.
Bit 2: EXT
, External Clock Bit.
Set 1: Timer 1 clock source from external
Set 0: Timer 1 clock source from internal
Bit 1 : ALT
, Alternate Compare Bit. This bit controls whether the timer runs in single or dual maximum count mode.
Set 1: Specify dual maximum count mode. In this mode the timer counts to Maxcount Compare A, then resets the
count register to 0. Then the timer counts to Maxcount Compare B, then resets the count register to 0 again,
and starts over with Maxcount Compare A.
Set 0: Specify single maximum count mode. In this mode the timer will count to the valve contained in Maxcount
Compare A and reset to 0, and then the timer counts to Maxcount Compare A again. Maxcount Compare B is
not used in this mode.
Bit 0: CONT
, Continuous Mode Bit.
Set 1: The timer to run continuously.
Set 0: The timer will halt after each counting to the maximum count and the EN bit will be cleared.
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