
R DC
8. Peripheral Control Block Register
The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
21
starts at FF00h in I/O space when reset the microprocessor.
The following table is the definition of all the peripheral Control Block Register , and the detail description will arrange on
the relation Block Unit.
Offset
(HEX)
FE
F6
F4
F2
F0
E6
E4
E2
E0
DA
D8
D6
D4
D2
D0
CA
C8
C6
C4
C2
C0
A8
A6
A4
A2
A0
88
86
84
82
80
7A
78
76
74
72
Register Name
Page
Offset
(HEX)
70
66
62
60
5E
5C
5A
58
56
54
52
50
44
42
40
3E
3C
3A
38
36
34
32
30
2E
2C
2A
28
26
24
22
20
18
16
14
12
10
Register Name
Page
Peripheral Control Block Relocation Register
Reset Configuration Register
Processor Release Level Register
Auxiliary configuration Register
System configuration register
Watchdog timer control register
Enable RCU Register
Clock Prescaler Register
Memory Partition Register
DMA 1 Control Register
DMA 1 Transfer Count Register
DMA 1 Destination Address High Register
DMA 1 Destination Address Low Register
DMA 1 Source Address High Register
DMA 1 Source Address Low Register
DMA 0 Control Register
DMA 0 Transfer Count Register
DMA 0 Destination Address High Register
DMA 0 Destination Address Low Register
DMA 0 Source Address High Register
DMA 0 Source Address Low Register
PCS and MCSAuxiliary Register
Midrange Memory Chip Select Register
Peripheral Chip Select Register
Low Memory Chip Select Register
Upper Memory Chip Select Register
Serial Port 0 Baud Rate Divisor Register
Serial Port 0 Receive Register
Serial Port 0 Transmit Register
Serial Port 0 Status Register
Serial Port 0 Control Register
PIO Data 1 Register
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
PIO Direction 0 Register
22
25
22
30
23
68
80
80
80
56
58
58
59
59
59
55
55
55
56
56
56
34
33
35
32
31
75
75
74
74
72
78
78
78
79
79
PIO Mode 0 Register
Timer 2 Mode / Control Register
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode / Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
Timer 0 Mode / Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
Serial Port 0 interrupt control register
Serial port 1 interrupt control register
INT4 Control Register
INT3 Control Register
INT2 Control Register
INT1 Control Register
INT0 Control Register
DMA 1/INT6 Interrupt Control Register
DMA 0/INT5 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
Interrupt In-service Register
InterruptPriority Mask Register
Interrupt Mask Register
Interrupt Poll Status Register
Interrupt Poll Register
Interrupt End-of-Interrupt
Interrupt Vector Register
Serial port 1 baud rate divisor
Serial port 1 receive register
Serial port 1 transmit register
Serial port 1 status register
Serial port 1 control register
79
65
66
66
63
65
65
65
62
63
63
62
40
41
42
42
43
43
44
45
45
46
47
47
48
49
50
51
51
52
52
76
76
76
75
75