
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
51
(Slave Mode)
Bit 15-6 :
Reserved.
Bit 5-4 : TMR2-TMR1
, Timer 2/Timer1 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control register.
Set 1: Timer2 or Time1 has its interrupt requests masked
Bit 3-2 : D1/I6-D0/I5
, DMA Channel or INT Interrupt Mask.
Indicating the state of the mask bits of the corresponding DMA or INT6/INT5 control register.
Bit 1 :
Reserved.
Bit 0 : TMR0
, Timer 0 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control Register
(Master Mode)
The Poll Status (POLLST) register mirrors the current state of the Poll register. the POLLST register can be read without
affecting the current interrupt request.
Bit 15 : IREQ
, Interrupt Request.
Set 1: if an interrupt is pending. The S4-S0 field contains valid data.
Bit 14-5 :
Reserved.
Bit 4-0 : S4-S0
, Poll Status. Indicates the interrupt type of the highest priority pending interrupt.
(Master Mode)
When the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register.
Bit 15 : IREQ
, Interrupt Request.
Set 1: if an interrupt is pending. The S4-S0 field contains valid data.
Poll Status Register
Offset : 26h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
S4 - S0
Reserved
IREQ
Poll Register
Offset : 24h
Reset Value :
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
S4 - S0
Reserved
IREQ
Interrupt Request Register
Offset : 28h
Reset Value : 003Dh
2
3
0
1
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
D0/I5
Res
TMR0
D1/I6
TMR1
TMR2