
R DC
11. Bus Interface Unit
The bus interface unit drives address, data, status and control information to define a bus cycle. The bus A19-A0 are non-
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
26
multiplex memory or I/O address. The AD15-AD0 are multiplexed address and data bus for memory or I/O accessing. The
2
S -S are encoded to indicate the bus status, which is described in the Pin Description table in page 5. The Basic
Application System Block (page 10) and Read/Write Timing Diagram (page 12) describe the basic bus operation.
11.1 Memory and I/O interface
The memory space consists of 1M bytes (512k 16-bit port) and the I/O space consists of 64k bytes (32k 16-bit port). Memory
devices exchange information with the CPU during memory read, memory write and instruction fetch bus cycles. I/O read
and I/O write bus cycles use a separate I/O address space. Only IN/OUT instruction can access I/O address space, and
information must be transferred between the peripheral device and the AX register. The first 256 bytes of I/O space can be
accessed directly by the I/O instructions. The entire 64k bytes I/O address space can be accessed indirectly, through the DX
register. I/O instructions always force address A19-A16 to low level.
11.2 Data Bus
The memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k
bytes. Each one bank connects to the lower half of the data bus and contains the even-addressed bytes (A0=0). The other
Memory
Space
FFFFFH
0
1M Bytes
I/O
Space
0FFFFH
0
64K Bytes
Memory and I/O Space
FFFFF
FFFFD
5
3
1
FFFFE
FFFFC
4
2
0
512K Bytes
512K Bytes
A19:1
D15:8
BHE
D7:0
A0
Physical Data Bus Models