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參數(shù)資料
| 型號： | R8820LV |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-BIT RISC MICROCONTROLLER |
| 中文描述： | 16位RISC微控制器 |
| 文件頁數(shù)： | 20/98頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | R8820LV |
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R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
20
Bit 9 : IF
, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag.
Set to 1 : The CPU enables the maskable interrupt request.
Set to 0 : The CPU disables the maskable interrupt request.
Bit 8: TF
, Trace Flag. Set to enable single-step mode for debugging; Clear to disable the single-step mode. If an application
program sets the TF flag using POPF or IRET instruction, a debug exception is generated after the instruction (The
CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction.
Bit 7
: SF, Sign Flag. If this flag is set, the high-order bit of the result of an operation is 1
,
indicating it is negative.
Bit 6: ZF
, Zero Flag. The result of operation is zero, this flag is set.
Bit 5
: Reserved
Bit 4: AF
, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble to the high or a borrow from the high
nibble to the low nibble of the AL general-purpose register. Used in BCD operation.
Bit 3
: Reserved.
Bit 2: PF
, Parity Flag. The result of low-order 8 bits operation has even parity, this flag is set.
Bit 1
: Reserved
Bit 0: CF
, Carry Flag. If CF is set, there has been a carry out or a borrow into the high-order bit of the instruction result.
7.4 Address generation
The Execution Unit generates a 20-bit physical address to Bus Interface Unit by the Address Generation. Memory is organized
in sets of segments. Each segment contains a 16 bits value. Memory is addressed using a two-component address that consists
of a 16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address transfers to the
physical address.
1
2
F
9
0
19
0
0
0
1
2
15
0
1
2
F
A
2
19
0
TO Memory
1
2
F
9
0
0
1
2
15
0
15
0
Physical Address
Segment Base
Offset
Logical
Address
Shift left 4 bits
Physical Address Generation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R8821 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8822 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RDC 16 Bit RISC MICRO-CONTROLLER |
| R8822I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830 | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
| R8830I | 制造商:RDC 制造商全稱:RDC 功能描述:16-BIT RISC MICROCONTROLLER |
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