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MB90560 series
APPENDIX B INSTRUCTIONS
503
B.5
Number of Execution Cycles
The number of cycles required to execute an instruction is obtained by adding the
number of cycles for the instruction, the compensation value determined by
conditions, and the number of cycles for program fetch.
I
Number of execution cycles
The number of cycles required to execute an instruction is obtained by adding the number of
cycles for the instruction, the compensation value determined by conditions, and the number of
cycles for program fetch.
Because a program in memory connected to the 16-bit bus to the built-in ROM is fetched each
time an executing instruction exceeds the word boundary, the number of execution cycles
increases if data access is interfered with.
Because a program in memory connected to the 8-bit external data bus is fetched for each byte
of the instruction being executed, the number of execution cycles increases if data access is
interfered with.
If general-purpose registers, built-in ROM, built-in RAM, built-in I/O, and external data buses are
accessed during intermittent operation of the CPU, clocks supplied to the CPU stop for the
number of cycles specified by the CG0 and CG1 bits of the low-power consumption mode
control register. To calculate the number of cycles needed to execute an instruction during
intermittent operation of the CPU, add as a compensation value to the normal number of
execution cycles the product of the number of accesses and the number of cycles for the
temporary stop.
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Calculation of the number of execution cycles
Tables B.5-1~ B.5-3 list the number of execution cycles for each instruction and compensation
values.
Table B.5-1 Number of execution cycles for each type of addressing
Code
Operand
(a) (*1)
Number of register
accesses for type of
addressing
Number of execution cycles for
type of addressing
00
|
07
Ri
RWi
RLi
Shown in instruction list.
Shown in instruction list.
08
|
0B
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWj+disp8
2
1