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16.4
16.4.1 A/D control status register 1 (ADCS1)
8/10-Bit A/D Converter Registers
MB90560 series
CHAPTER 16 8/10-BIT A/D CONVERTER
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
I
Upper bits of the A/D control status register (ADCS1)
Figure 16.4-2 A/D control status register 1 (ADCS1)
PAUS
(ADCS0)
STS1
STRT RESV
STS0
INTE
0
1
Interrupt request enable bit
Disables interrupt request output.
Enables interrupt request output.
BUSY
INT
INTE
INT
Interrupt request flag bit
Reading
Busy bit
A/D conversion has not been completed.
A/D conversion has been completed.
A/D conveision is halted.
A/D conversion is in progress.
Clears this bit.
No change,no effect on other bits.
Stops the A/D conversion.
No change,no effect on other bits.
0
1
Writing
Reading
Writing
BUSY
0
1
STRT
A/D conversion activation bit
(
valid only when activated by software (ADC2: EXT= 0))
Reserved bit
RESV
Always write 0 to this bit.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
STS1STS0
0
0
1
A/D activation select bit
Activation by software.
Activation by external trigger or software.
Activation by timer or software.
Activation by external trigger, timer, or
software.
1
0
1
0
1
Does not activate the A/D conversion.
Activate the A/D conversion function.
0
1
PAUS
Halt flag bit
(valid only when EI
2
OS is used)
A/D conversion is not halted.
A/D conversion is halted.
0
1
000035
H
00000000
B
R/W
W
-
: Read/write
: Write only
: Undefined
: Initial value
bit15
Address
Initial value
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit0