![](http://datasheet.mmic.net.cn/330000/MB90F562_datasheet_16437954/MB90F562_137.png)
MB90560 series
CHAPTER 5 LOW POWER CONSUMPTION MODE
113
I
Low power consumption mode operating states
Table 5.6-1 lists the operating states of low power consumption mode.
Table 5.6-1 Low power consumption mode operating states
G
Clock mode switching and release (excluding standby mode)
Table 5.6-2 lists clock mode switching and release.
Table 5.6-2 Clock mode switching and release
*1The microcontroller operates using the main clock during the PLL clock oscillation stabilization
wait state.
Low power
consumption
mode
Condition
for
transition
Oscil-
lation
Clock
CPU
Peripheral
Pin
Release
event
Main sleep
MCS = 1
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
PLL sleep
MCS = 0
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
Timebase timer
(SPL = 0)
MCS = 0
STP = 1
Active
Inactive
Inactive
Inactive
Hold
Reset or
interrupt
Timebase timer
(SPL = 1)
MCS = 0
STP = 1
Active
Inactive
Inactive
Inactive
Hi-z
Reset or
interrupt
Stop (SPL = 0)
MCS = 1
STP = 1
Inactive
Inactive
Inactive
Inactive
Hold
Reset or
interrupt
Stop (SPL = 1)
MCS = 1
STP = 1
Inactive
Inactive
Inactive
Inactive
Hi-z
Reset or
interrupt
Transition
Conditions
After power-on, transition to
the main run state
[1] Source clock oscillation stabilization wait interval ends. (Timebase
timer output)
[2] Reset input has been cleared.
Reset during main run state
[3] External reset, software reset, or watchdog timer reset
Transition from main run
state to PLL run state
[4]
MCS = 0 (After PLL clock oscillation stabilization wait, switch to PLL
clock) (*1)
Return to main run state from
PLL run state
[5]
MCS = 1 (PLL clock deactivated)
Reset during PLL run state
[6] External reset or software reset ([7] After reset, return to PLL run
state)
[8] Watch dog reset ([3] After reset, return to main run state)