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CHAPTER 5 LOW POWER CONSUMPTION MODE
MB90560 series
5.5
5.5.1 Sleep mode
Standby Mode
Sleep mode causes the CPU operating clock to stop while other peripheral functions
continue to operate.
When the low power mode control register (LPMCR) indicates a switch to sleep mode,
a switch to PLL sleep mode occurs if PLL clock mode has been set. Alternatively, a
switch to main sleep mode occurs if main clock mode has been set.
I
Switching to sleep mode
Writing “1” to the SLP bit of LPMCR and “0” to the STP bit of LPMCR triggers a switch to sleep
mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is “0”, the microcontroller
enters PLL sleep mode. If the MCS bit of CKSCR is “1”, the microcontroller enters main sleep
mode.
<Check>
Since the STP bit setting overrides the SLP bit setting when “1” is written to the SLP and STP
bits at the same time, the mode switches to timebase timer mode or stop mode.
G
Data retention function
In sleep mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
G
Operation during an interrupt request
Writing “1” to the SLP bit of LPMCR during an interrupt request does not switch to sleep mode. If
the CPU does not accept the interrupt, the CPU executes the next instruction. If the CPU
accepts the interrupt, CPU operation immediately branches to the interrupt processing routine.
G
Status of pins
During sleep mode, all pins retain the state they had immediately before the switch to sleep
mode.
I
Release of sleep mode
The low power consumption control circuit is used to release sleep mode. Releasing is caused
by the input of a reset or by an interrupt.
G
Return to normal mode by a reset
When sleep mode is released by a reset, the microcontroller is placed in the reset state on
release from sleep mode.