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MB90560 series
CHAPTER 16 8/10-BIT A/D CONVERTER
435
G
A/D control status register (ADCS1, 2)
This register selects activation by software or another activation trigger, the conversion mode,
and the A/D conversion channel. It also enables or disables interrupt requests, checks the
interrupt request status, and indicates whether the conversion has halted or is in progress.
G
A/D data register (ADCR1,2)
This register holds the result of A/D conversion and selects the resolution for A/D conversion.
G
Clock selector
The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer
channel 1 output or 16-bit free-running timer zero detection can be used as the activation clock.
G
Decoder
This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2
bits and ANS0 to ANS2 bits of the A/D control status register (ADCS1).
G
Analog channel selector
This circuit selects the pin to be used from eight analog input pins.
G
Sample hold circuit
This circuit holds the input voltage of the channel selected by the analog channel selector. It
samples and holds the input voltage obtained immediately after the activation of A/D conversion.
This circuit protects the A/D conversion from any variations in the input voltage during
approximation.
G
D/A converter
This circuit generates a reference voltage for comparison with the input voltage maintained by
the sample hold circuit.
G
Comparator
This circuit compares the input voltage held by the sample hold circuit with the output voltage of
the D/A converter to determine which is greater.
G
Control circuit
This circuit determines the A/D conversion value based on the decision signal generated by the
comparator. When the A/D conversion has been completed, the circuit sets the conversion result
in the A/D data register (ADCR1, 2) and generates an interrupt request.