
MB90560 series
CHAPTER 1 OVERVIEW
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Sleep mode (in which the CPU operating clock stops)
Time-base timer mode (in which only the source oscillation and time-base timer are
active)
Stop mode (in which the source oscillation stops)
CPU intermittent operation mode
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Packages
QFP-64 (FPT-64P-M09: 0.65 mm pin pitch, FPT-64P-M06: 1.00 mm pin pitch)
SH-DIP (DIP-64-M01: 1.778 pin pitch)
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Process : CMOS technology
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Internal peripheral functions (resources)
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I/O ports: Up to 50 posts
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18-bit time-base timer: 1 channel
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Watchdog timer: 1 channel
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16-bit reload timer: 2 channels
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Advanced timer: 1 channel
16-bit free running timer: 1 channel
16-bit output compare: 6 channels
When the count of the 16-bit free running timer matches the count set for comparison, the
output compare unit inverts the output and generates an interrupt request.
16-bit input capture: 4 channels
When the edge of the pin input is detected, the input capture unit latches the count of the
16-bit free running timer and generates an interrupt request.
8-/16-bit PPG timer: 8 bits x 6 channels or 16 bits x 3 channels
Capable of changing the period or duty cycle of the output pulses as desired.
Waveform generation circuit (8-bit timer: 3 channels)
Capable of generating optimum waveforms for inverter control.
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UART: 2 channels
With full duplex double buffer (8-bit length)
Capable of asynchronous or synchronous transfer (I/O extended serial)
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DTP/external interrupt (8 channels)
Module for activating the extended intelligent I/O service by external input and for generating
an external interrupt
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Delayed interrupt generator module
Generates an interrupt request for task switching.
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8/10-bit A/D converter (8 channels)
Selectable resolution of 8 or 10 bits
Capable of activation by external trigger