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CHAPTER 6 INTERRUPTS
MB90560 series
6.4
6.4.5 Hardware interrupt processing time
Hardware Interrupts
From the occurrence of a hardware interrupt request to the execution of an interrupt
processing routine, the time for the instruction currently being executed to terminate
and the time required to handle an interrupt are necessary.
I
Hardware interrupt processing time
From the occurrence of a hardware interrupt request to the acceptance of the interrupt and to
the execution of an interrupt processing routine, the time to wait for sampling for an interrupt
request and the time required to handle an interrupt (time to prepare for interrupt processing) are
necessary. Figure 6.4-6 shows the interrupt processing time.
Figure 6.4-6 Interrupt processing time
G
Interrupt request sampling wait time
The interrupt request sampling wait time is the time from the occurrence of and interrupt request
to the termination of the instruction currently being executed.
Whether an interrupt request has been occurred is determined by sampling the instruction for an
interrupt request during execution of each instruction creating a delay.
<Reference>
The interrupt request sampling wait time is the maximum when an interrupt request is
generated as soon as the POPW RW0, ... RW7 instruction (45 machine cycles), which takes
the longest to execute, starts.
CPU operation
Interrupt wait time
Interrupt request generation
Ordinary instruction
execution
Interrupt request
sampling wait time
Interrupt handling
Interrupt processing
routine
Interrupt handling time
(
θ
machine cycle) (*1)
: The final instruction cycle samples the interrupt request here.
: One machine cycle corresponds to one machine clock (
φ
).