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CHAPTER 11 16-BIT RELOAD TIMER
MB90560 series
11.5 16-Bit Reload Timer Interrupts
The 16-bit reload timer is able to generate an interrupt request when an underflow of
the counter is occurred. It is also coordinated with the extended intelligent I/O service
(EI
2
OS).
I
16-bit reload timer interrupts
Table 11.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer.
Table 11.5-1 Interrupt control bits and interrupt causes of the 16-bit reload timer
In the 16-bit reload timer, the UF bit of the timer control status register (TMCSR) is set to 1 by an
underflow (from 0000
H
to FFFF
H
) of the down counter. If an interrupt request is enabled
(TMCSR: INTE = 1) in this operation, the interrupt request is output to the interrupt controller.
I
16-bit reload timer interrupts and EI
2
OS
Table 11.5-2 lists the 16-bit reload timer interrupts and EI2OS.
Table 11.5-2 16-bit reload timer interrupts and EI
2
OS
: Available when ICR09 or the interrupt causes sharing the interrupt vector are not used.
*1 The same interrupt number as that for 8-bit timer counter underflow and 16-bit reload timer 0
underflow.
*2 The same interrupt number as that for 16-bit free-run timer overflow and 16-bit reload timer 1
underflow.
16-bit reload timer 0
16-bit reload timer 1
Interrupt request flag bit
TMCSR0: UF
TMCSR1: UF
Interrupt request enable bit
TMCSR0: INTE
TMCSR: INTE
Interrupt cause
Underflow of the 16-bit down
counter (TMR0
)
Underflow of the 16-bit down
counter (TMR1)
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI
2
OS
Register
name
Address
Lower
Upper
Bank
16-bit reload
timer 0 (*1)
#30 (1E
H
)
ICR09
0000B9
H
FFFF84
H
FFFF85
H
FFFF86
H
16-bit reload
timer 1 (*2)
#32 (20
H
)
ICR10
0000BA
H
FFFF7C
H
FFFF7D
H
FFFF7E
H