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CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION
MB90560 series
[bit0]: Address Detect Register0’s is Detected (AD0D)
ADR0 address match detection bit. This bit is set to “1” to indicate that the value set in the
PADR0 register is equal to the address. It is cleared to “0” by writing “0” to it. It is left unchanged
by writing “1” to it.
I
Operation of the Address Match Detection Function
An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code
(01
H
) when the corresponding address is equal to the value set in an address detection register.
Therefore, the CPU executes the INT9 instruction when executing the set instruction.
A program patch application function can be implemented by processing with the INT #9
interrupt routine.
There are two address detection registers, of which each is provided with an interrupt enable bit
and interrupt flag. When the address is equal to the value set in the address detection register,
and the interrupt enable bit is “1”, assume the following: the interrupt flag is set to “1”, and the
instruction code to be read by the CPU is replaced forcibly with the INT9 instruction code. The
interrupt flag is cleared to “0” by writing “0” to it using an instruction.
I
Notes on the Address Match Detection Function
The address match detection function fails if an address later than the first byte of the instruction
is set in the address detection register. The value in the set address is replaced with 01
H
so a
wrong instruction is executed or an invalid address is accessed. Before changing the value set in
the address detection register, set the interrupt enable bit to “0”. If data is written while the
interrupt enable bit is “1”, the address may be wrongly detected during writing, causing a
malfunction.