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CHAPTER 11 16-BIT RELOAD TIMER
MB90560 series
11.4
16-Bit Reload Timer Registers
11.4.2 Timer control status register, lower part (TMCSR0, TMCSR1: L)
The lower seven bits of the timer control status registers (TMCSR0 and TMCSR1) are
used to set operating conditions for the 16-bit reload timer, enable and disable
operation, control interrupts, and check the status.
I
Timer control status register, low part (TMCSR0, TMCSR1: L)
Figure 11.4-3 Timer control status register, low part (TMCSR0, TMCSR1: L)
Address
TMCSR0
000082
H
TMCSR1
000086
H
Initial value
00000000
B
MOD0*OUTE OUTL RELD
INTE
UF
CNTE TRG
(TMCSR:H
bit15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit8
bit6
bit7
bit5
bit4
bit3
bit2
bit1
bit0
TRG
0
No change, no effect on other bits
After reloading, counting starts.
1
Software trigger bit
INTE
0
Interrupt request output disabled
Interrupt request output enabled
1
Interrupt request enable bit
RELD
0
One-shot mode
Reload mode
1
Reload selection bit
CNTE
0
Counting stopped
Counting enabled (wait for the start trigger)
1
Count enable bit
UF
During reading
Without counter underflow
During writing
Underflow interrupt request flag bit
0
With counter underflow
This bit is cleared.
No change, no effect on other bits
1
OUTL
In single-shot mode (RELD = 0)
In reload mode (RELD = 1)
Pin output level selection bit
0
Square wave of H during counting
Square wave of L during count
Toggle output of L when counting is started.
Toggle output of H when counting is started.
1
OUTE
Pin functions
Registers and pins corresponding to each channel
TMCSR0
P21
TO0
P23
TO1
TMCSR1
Timer output enable bit
0
General-purpose port
Timer output
1
R/W: Read/write
: Initial value
* : See Section 10.4.1, "Timer control status register, high part," for MOD0 (bit 7)