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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 8/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
8
AN1283/D
Maskable interrupt sources have the following priorities:
1. IRQ Interrupt
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system
Any single interrupt source can be designated as the highest-priority interrupt by writing an appropriate val-
ue to the PSEL bits in the HPRIO register. Priority relationships of other maskable interrupts remain the
same. An interrupt that is assigned highest priority is still subject to global masking by the I bit. Interrupt
vectors are not affected by priority assignment.
3 CPU16 MODULE
The M68HC16 central processing unit (CPU16) was designed to provide compatibility with the M68HC11
CPU and to provide additional capabilities associated with 16- and 32-bit data sizes, 20-bit addressing, and
digital signal processing.
The CPU16 treats all peripheral, I/O, and memory locations as parts of a pseudolinear 1 Megabyte address
space. There are no special instructions for I/O that are separate from instructions for addressing memory.
Address space is made up of 16 64-Kbyte banks. Specialized bank addressing techniques and support reg-
isters provide transparent access across bank boundaries.
The CPU16 interacts with external devices and with other modules within the microcontroller via a standard-
ized bus and bus interface. There are bus protocols for memory and peripheral accesses, as well as for
managing an hierarchy of interrupt priorities.
3.1 Programming Model
CPU16 registers are an integral part of the CPU and are not addressed as memory locations. The CPU16
register model contains all the resources of the M68HC11 CPU, plus additional resources.
the CPU16 programming model. Registers are discussed in detail in the following paragraphs.
Figure 3
shows
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