參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 19/52頁(yè)
文件大?。?/td> 358K
代理商： M68HC16
AN1283/D
MOTOROLA
19
3.12 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. M68HC16 microcon-
trollers perform resets with a combination of hardware and software. The system integration module deter-
mines whether a reset is valid, asserts control signals, performs basic system configuration and boot ROM
selection based on hardware mode-select inputs, then passes control to the CPU16.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated by
the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset can oc-
cur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there is no clock
when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in order to allow
completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU16 exception. Any processing in progress is aborted by the reset exception,
and cannot be restarted. Only essential tasks are performed during reset exception processing. Other ini-
tialization tasks must be accomplished by the exception handler routine.
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the
state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what
happens during subsequent breakpoint assertions.
Generally, module pins default to port functions, and input/output ports are set to input state. This is accom-
plished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port
data direction registers.
3.12.1 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External RE-
SET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor
timeout period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM
pins are either in an inactive, high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into an
internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it de-
tects that the RESET signal is no longer being externally driven, to guarantee this length of reset to the en-
tire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512 cy-
cles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert RESET
until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cycles.
At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one, reset excep-
tion processing begins. If, however, the reset input is at logic level zero, the reset control logic drives the pin
low for another 512 cycles. At the end of this period, the pin again goes to high-impedance state for 10 cy-
cles, then it is tested again. The process repeats until RESET is released.
During power-on reset, an internal circuit in the SIM drives the IMB internal and external reset lines. The
circuit releases the internal reset line as V
DD
ramps up to the minimum specified value, and SIM pins are
initialized. When V
DD
reaches the specified minimum value, the clock synthesizer VCO begins operation.
Clock frequency ramps up to the specified limp mode frequency. The external RESET line remains asserted
until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and
the internal reset signal is asserted for four clock cycles, these modules reset. V
DD
ramp time and VCO fre-
quency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds.
During this period, module port pins may be in an indeterminate state. While input-only pins can be put in a
known state by means of external pull-up resistors, external logic on input/output or output-only pins must
condition the lines during this time. Active drivers require high-impedance buffers or isolation resistors to
prevent conflict.
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