參數(shù)資料
型號： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁數(shù)： 30/52頁
文件大?。?/td> 358K
代理商： M68HC16
MOTOROLA
30
AN1283/D
5 COMPARISON OF ADDRESSING MODES
In general, CPU16 addressing modes can be thought of as a superset of M68HC11 CPU addressing
modes. The CPU16 has all the capabilities of the M68HC11 CPU, and each mode is enhanced by the
pseudolinear addressing scheme. In addition, M68HC11 direct addressing has been replaced by an en-
hanced form of indexed addressing that can use the IZ register as a pointer out of reset.
5.1 Addressing Mode Differences
The following paragraphs summarize the differences between CPU16 addressing modes and the equiva-
lent M68HC11 CPU addressing modes. In addition, the effects discussed in
3.7 CPU16 Pipeline Mecha-
nism
must be considered when indexed modes are used.
5.1.1 Extended Addressing Mode
In M68HC11 CPU extended addressing mode, the effective address of the instruction appears explicitly in
the two bytes following the opcode. In CPU16 extended addressing mode, the effective address is formed
by concatenating the EK field and the 16-bit byte address. A 20-bit extended mode (EXT20) is used only by
the JMP and JSR instructions. These instructions contain a 20-bit effective address that is zero-extended
to 24 bits to give the instruction an even number of bytes.
5.1.2 Indexed Addressing Mode
M68HC11 CPU indexed addressing mode forms the effective address by adding an 8-bit unsigned offset to
the index register. In CPU16 indexed addressing mode, a 16-bit offset can be used. However, the 16-bit
offset is signed and effective address calculation can yield a negative offset from the index register. An 8-
bit unsigned mode is still available on the CPU16. A 20-bit indexed mode is used for JMP and JSR instruc-
tions. In 20-bit modes, a 20-bit signed offset is added to the value contained in an index register.
5.1.3 Post-Modified Index Addressing Mode
Post-modified index mode is used with the CPU16 MOVB and MOVW instructions. A signed 8-bit offset is
added to index register X after the effective address formed by XK : IX is used.
5.2 Use Of CPU16 Indexed Mode To Replace M68HC11 Direct Mode
In M68HC11 systems, direct addressing mode can be used to perform rapid accesses to RAM or I/O
mapped into bank 0 ($0000 to $00FF), but the CPU16 uses the first 512 bytes of bank 0 for exception vec-
tors. To provide an enhanced replacement for direct mode, the ZK field and index register Z have been as-
signed reset initialization vectors. After ZK : IZ have been initialized, indexed addressing can provide rapid
access to any address in the memory map.
6 INSTRUCTION SET REFERENCE
Table 8
and
Table 9
are comprehensive references to the M68HC11 CPU and the CPU16 instructions sets.
For more detailed information, please refer to the M68HC11 Reference Manual(M68HC11RM/AD) and to
the CPU16 Reference Manual(CPU16RM/AD).
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