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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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AN1283/D
MOTOROLA
15
There are three functional blocks involved in fetching, decoding, and executing instructions. These are the
microsequencer, the instruction pipeline, and the execution unit. These elements function concurrently —
at any given time, all three may be active.
3.7.1 Microsequencer
The microsequencer controls the order in which instructions are fetched, advanced through the pipeline,
and executed. It increments the program counter and generates multiplexed external tracking signals
IPIPE0 and IPIPE1 from internal signals that control execution sequence.
3.7.2 Instruction Pipeline
The pipeline is a three stage FIFO that holds instructions while they are decoded and executed. As many
as three instructions can be in the pipeline at one time (single-word instructions, one held in stage C, one
being executed in stage B, and one latched in stage A).
3.7.3 Execution Unit
The execution unit evaluates opcodes, interfaces with the microsequencer to advance instructions through
the pipeline, and performs instruction operations.
3.8 Execution Process
A prefetch mechanism in the microsequencer reads instruction words from memory and increments the pro-
gram counter. When instruction execution begins, the program counter points to an address six bytes after
the address of the first word of the instruction being executed.
Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are evaluated in stage B.
The execution unit can access operands in either stage A or stage B (stage B accesses are limited to 8-bit
operands). When execution is complete, opcodes are moved from stage B to stage C, where they remain
until the next instruction is complete. The number of machine cycles necessary to complete an execution
sequence varies according to the complexity of the instruction.
3.9 Changes in Program Flow
When program flow changes, instructions are fetched from a new address. Before execution can begin at
the new address, instructions and operands from the previous instruction stream must be removed from the
pipeline. If a change in flow is temporary, a return address must be stored, so that execution of the original
instruction stream can resume after the change in flow.
At the time an instruction that causes a change in program flow executes, PK : PC point to the address of
the first word of the instruction
+
$0006. During execution of the instruction, PK : PC is loaded with the ad-
dress of the first word of the new instruction stream. However, stages A and B still contain words from the
old instruction stream. The CPU16 prefetches to advance the new instruction to stage C, and fills the pipe-
line from the new instruction stream.
3.9.1 Jumps
The CPU16 jump instruction uses 20-bit extended and indexed addressing modes. It consists of an 8-bit
opcode with a 20-bit argument. No return PK : PC is stacked for a jump.
3.9.2 Branches
The CPU16 supports 8-bit relative displacement (short), and 16-bit relative displacement (long) branch in-
structions, as well as specialized bit condition branches that use indexed addressing modes. CPU16 short
branches are generally equivalent to M68HC11 CPU branches, although opcodes are not identical.
M68HC11 BHI and BLO are replaced by CPU16 BCC and BCS.
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