參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 3/52頁(yè)
文件大小： 358K
代理商： M68HC16
AN1283/D
MOTOROLA
3
I — Interrupt Mask
I is a global mask that disables maskable interrupt sources. While I is set, no maskable interrupts are
processed. After reset, I is set and can only be cleared by software. I is normally cleared when CCR
content is restored by the RTI instruction at the end of an interrupt service routine.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two's complement overflow occurs as the result of an operation.
C — Carry Flag
Set when carry or borrow occurs during arithmetic operation. Also used during shift and rotate
2.2 Memory Management
All M68HC11 devices have a contiguous 64 Kbyte address space that is accessed by means of a 16-line
address bus. Some devices have the upper eight address lines multiplexed with the data bus lines, while
others have non-multiplexed address and data buses. Some variants also have address extension capabil-
ities — the CPU address space remains 64 Kbytes, but on-chip logic and extra address lines are provided
to implement bank-switching in external memory. Extended memory is accessed by means of two windows
of a pre-defined size and extend.
2.3 Data Types
The M68HC11 CPU supports the following data types:
Bit data
8-bit and 16-bit signed and unsigned integers
16-bit unsigned fractions
16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes with the most significant byte at the lower value address. Because the M68HC11 CPU is an 8-bit CPU,
there are no special requirements for alignment of instructions or operands.
2.4 Addressing Modes
The M68HC11 CPU uses six basic types of addressing. Each type consists of one or more addressing
modes. All modes except inherent mode use an effective address. The effective address is the memory ad-
dress from which an argument is fetched or stored, or the address from which execution is to proceed. An
effective address can be specified within an instruction, or it can be calculated.
M68HC11 CPU addressing modes.
Table 1
shows the various
Table 1 M68HC11 CPU Addressing Modes
Mode
Direct
Extended
Immediate
Mnemonic
DIR
EXT
IMM
IND, X
IND, Y
INH
Description
Low-order byte of effective address follows opcode
Effective address follows opcode
Argument follows opcode
Effective address formed by adding unsigned 8-bit offset from instruc-
tion to index register content
Opcode contains information necessary for execution
When a branch is taken, effective address formed by adding signed 8-
bit offset from instruction to PC content.
Indexed
Inherent
Relative
REL
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