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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
18
AN1283/D
3.10.4 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which are defined as asyn-
chronous, include interrupts, bus errors, breakpoints, and resets. Internal exceptions, which are defined as
synchronous, include the software interrupt (SWI) instruction, the background (BGND) instruction, illegal in-
struction exceptions, and the divide-by-zero exception.
3.10.4.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception processing is syn-
chronized. For all asynchronous exceptions but reset, exception processing begins at the first instruction
boundary following recognition of an exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than reset,
is equal to the address of the next instruction in the current instruction stream plus $0006. The RTI instruc-
tion, which must terminate all exception handler routines, subtracts $0006 from the stacked value in order
to resume execution of the interrupted instruction stream.
3.10.4.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for synchronous
exceptions will always be completed, and the first instruction of the handler routine will always be executed,
before interrupts are detected.
Because of pipelining, the value of PK : PC at the time a synchronous exception executes is equal to the
address of the instruction that causes the exception plus $0006. Since RTI always subtracts $0006 upon
return, the stacked PK : PC must be adjusted so that execution will resume with the following instruction.
For this reason $0002 is added to the PK : PC value before it is stacked.
3.10.4.3 Multiple Exceptions
Each exception has a hardware priority based upon its relative importance to system operation. Asynchro-
nous exceptions have higher priorities than synchronous exceptions. Exception processing for multiple ex-
ceptions is done by priority, from lowest to highest. Priority governs the order in which exception processing
occurs, not the order in which exception handlers are executed.
Unless a bus error, a breakpoint, or a reset occurs during exception processing, the first instruction of all
exception handler routines is guaranteed to execute before another exception is processed. Since interrupt
exceptions have higher priority than synchronous exceptions, this means that the first instruction in an in-
terrupt handler will be executed before other interrupts are sensed.
Bus error, breakpoint, and reset exceptions that occur during exception processing of a previous exception
are processed before the first instruction of that exception's handler routine. The converse is not true — if
an interrupt occurs during bus error exception processing, for example, the first instruction of the bus error
handler is executed before interrupts are sensed. This permits the exception handler to mask interrupts dur-
ing execution.
3.11 RTI Instruction
The return-from-interrupt (RTI) instruction is used to terminate all exception handlers except the reset han-
dler. RTI restores context so that normal execution can resume. Asynchronous interrupts are serviced at
instruction boundaries, and a value of PK : PC
+
$0006 is stacked when exception processing begins. RTI
subtracts $0006 from the stacked value so that the pipeline is refilled from the correct address. RTI is not
used in the reset handler because the system is re-initialized and there is no context to restore.
SWI initiates interrupt exception processing without an external service request. The PK : PC value at the
time of execution is the first word address of SWI plus $0006. If this value were stacked, execution of RTI
at the end of the handler would cause SWI to execute again. To prevent this, SWI adds $0002 to the PK :
PC value prior to stacking.
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