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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
28
AN1283/D
4.3 Instructions With Transparent Changes
Some CPU16 instructions with mnemonics identical to M68HC11 instructions function differently than the
corresponding M68HC11 instructions, but accomplish the equivalent operation. These instructions are dis-
cussed in the following paragraphs.
4.3.1 RTS
The CPU16 stack frame differs from the M68HC11 CPU stack frame. PK : PC is restored during an RTS.
The PK field in the CCR is restored, then the PC value read from the stack is decremented by two before
being loaded into the PC. The PC value is decremented because LBSR and JSR are two-word instructions.
In order for program execution to resume with the instruction immediately following them, RTS must sub-
tract $0002 from the stacked PK : PC value. Because BSR is a one-word instruction, it subtracts $0002 from
PK : PC prior to stacking so that execution will resume correctly after RTS.
4.3.2 TSX
The CPU16 adds 2 to SK : SP before the transfer to XK : IX. The M68HC11 CPU adds 1.
4.3.3 TSY
The CPU16 adds 2 to SK : SP before the transfer to YK : IY. The M68HC11 CPU adds 1.
4.3.4 TXS
The CPU16 subtracts 2 from XK : IX before the transfer to SK : SP. The M68HC11 CPU subtracts 1.
4.3.5 TYS
The CPU16 subtracts 2 from YK : IY before the transfer to SK : SP. The M68HC11 CPU subtracts 1.
4.4 Unimplemented Instructions
There is only one M68HC11 instruction that has no CPU16 equivalent.
4.4.1 TEST
Causes the program counter to be continuously incremented.
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