參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 358K
代理商： M68HC16
AN1283/D
MOTOROLA
17
Figure 5 Exception Stack Frame Format
3.10.3 Exception Processing Sequence
Exception processing is performed in four distinct phases.
1. Priority of all pending exceptions is evaluated, and the highest priority exception is processed first.
2. Processor state is stacked, then the CCR PK extension field is cleared.
3. An exception vector number is acquired and converted to a vector address.
4. The content of the vector address is loaded into the PC, and the processor jumps to the exception
handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but the reset
vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be located within
Bank 0 or vectors must point to a jump table.
Table 6 Exception Vector Table
Vector
Number
0
Vector
Address
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012 – 001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032 – 006E
0070 – 01FE
Address
Space
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Type of
Exception
Reset — Initial ZK, SK, and PK
Reset — Initial PC
Reset — Initial SP
Reset — Initial IZ
Breakpoint
Bus Error
Software Interrupt Instruction (SWI)
Illegal Instruction
Division by Zero
Unassigned, Reserved
Uninitialized Interrupt
Unassigned, Reserved
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Spurious Interrupt
Unassigned, Reserved
User-Defined Interrupts
4
5
6
7
8
9 – E
F
10
11
12
13
14
15
16
17
18
19 – 37
38 – FF
Low Address
SP After Exception Stacking
Condition Code Register
Program Counter
High Address
SP Before Exception Stacking
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