參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 22/52頁(yè)
文件大?。?/td> 358K
代理商： M68HC16
MOTOROLA
22
AN1283/D
3.14 Development Support
The CPU16 incorporates powerful tools for tracking program execution and for system debugging. These
tools are deterministic opcode tracking, breakpoint exceptions, and background debugging mode. Judicious
use of CPU16 capabilities permits in-circuit emulation and system debugging using a bus state analyzer, a
simple serial interface, and a terminal. Refer to CPU16 Reference Manual(CPU16RM/AD) for more infor-
mation.
4 COMPARISON OF INSTRUCTION SETS
This section provides detailed analysis of differences between M68HC11 instructions and CPU16 instruc-
tions. Topics include functionally equivalent instructions, instructions with the same mnemonic that operate
differently, functions that perform the same operation in a different way, and unimplemented instructions.
4.1 Functionally Equivalent Instructions
The CPU16 has a number of instructions that are functionally equivalent to M68HC11 instructions — a
CPU16 instruction with a different mnemonic that performs the same task as an M68HC11 instruction. The
following paragraphs give the mnemonic of the M68HC11 instruction, then discuss the equivalent CPU16
operation.
4.1.1 BHS
The BHS mnemonic is used in the M68HC11 CPU instruction set to differentiate a branch based on a com-
parison of unsigned numbers from a branch based on operations that clear the Carry bit. The CPU16 uses
only the BCC mnemonic.
4.1.2 BHO
The BLO mnemonic is used in the M68HC11 CPU instruction set to differentiate a branch based on a com-
parison of unsigned numbers from a branch based on operations that set the Carry bit. The CPU16 uses
only the BCS mnemonic.
4.1.3 CLC
The CLC instruction has been replaced by ANDP. ANDP performs AND between the content of the condi-
tion code register and an unsigned immediate operand, then replaces the content of the CCR with the result.
The PK extension field (CCR[3:0]) is not affected.
The following code can be used to clear the C bit in the CCR:
ANDP #$FEFF
The ANDP instruction can clear the entire CCR, except for the PK extension field, at once.
4.1.4 CLI
The CLI instruction has been replaced by ANDP. ANDP performs AND between the content of the condition
code register and an unsigned immediate operand, then replaces the content of the CCR with the result.
The PK extension field (CCR[3:0]) is not affected.
The following code can be used to clear the IP field in the CCR:
ANDP #$FF1F
The ANDP instruction can clear the entire CCR, except for the PK extension field, at once.
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