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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
26
AN1283/D
LPSTOP operation is controlled by the S bit in the CCR. If S = 0 when LPSTOP is executed, the IP field
from the condition code register is copied into an external bus interface, and the MCU system clock is dis-
abled. If S = 1, LPSTOP operates in the same way as a 4-cycle NOP. The CPU16 initiates low-power stop,
but it and other controller modules are deactivated by the microcontroller system integration module. Reac-
tivation is also handled by the integration module. When a reset or an interrupt of higher priority than the IP
value occurs, the integration module activates the CPU16, and the appropriate exception processing se-
quence begins.
When WAI is executed, internal CPU clocks are stopped, and normal execution of instructions ceases. The
IP field is not copied to the integration module. System clocks continue to run. The processor waits until a
reset or an interrupt of higher priority than the IP value occurs, then begins the appropriate exception pro-
cessing sequence. Because the system integration module does not restart the CPU16, interrupts are ac-
knowledged more quickly following WAI than following LPSTOP.
4.2 Instructions That Operate Differently
There are a number of CPU16 instructions that have the same mnemonic as an M68HC11 instruction, but
operate differently. The following paragraphs discuss the differences in detail.
4.2.1 BSR
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16 stacks the current PC
and CCR, but restores only the return PK : PC. The programmer must designate (PSHM) which other reg-
isters are stacked during a subroutine. Because SK : SP point to the next available word address, stacked
CPU16 parameters are at a different offset from the stack pointer than stacked M68HC11 CPU parameters.
In order for RTS to work with all three calling instructions, the PK : PC value stacked by BSR is decremented
by two before being pushed on to the stack. Stacked PC value is the return address + $0002.
4.2.2 JSR
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16 stacks the current PC
and CCR, but restores only the return PK : PC. The programmer must designate (PSHM) which other reg-
isters are stacked during a subroutine. Because SK : SP point to the next available word address, stacked
CPU16 parameters are at a different offset from the stack pointer than stacked M68HC11 CPU parameters.
4.2.3 PSHA, PSHB
These instructions operate in the same way as the M68HC11 CPU instructions with the same mnemonics.
However, because the CPU16 normally pushes words from an even boundary, pushing byte data to the
stack can misalign the stack pointer and degrade performance.
4.2.4 PULA, PULB
These instructions operate in the same way as the M68HC11 CPU instructions with the same mnemonics.
However, because the CPU16 normally pulls words from the stack, pulling byte data can misalign the stack
pointer and degrade performance.
4.2.5 RTI
The CPU16 stack frame differs from the M68HC11 CPU stack frame. The CPU16 stacks only the current
PC and
CCR
before exception processing begins. In order to resume execution after interrupt with the cor-
rect instruction, RTI subtracts $0006 from the stacked PK : PC.
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