參數(shù)資料
型號: M68HC16
廠商: Motorola, Inc.
英文描述: 16-Bit Microcontroller(16位微控制器)
中文描述: 16位微控制器(16位微控制器)
文件頁數(shù): 34/52頁
文件大小: 358K
代理商: M68HC16
MOTOROLA
34
AN1283/D
JSR (opr)
Jump to
Subroutine
See Figure 3–2
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
9D
BD
AD
AD
86
96
B6
A6
A6
C6
D6
F6
E6
E6
CC
DC
FC
EC
EC
8E
9E
BE
AE
AE
CE
DE
FE
EE
EE
CE
DE
FE
EE
EE
78
68
68
48
18
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
LDAA (opr)
Load
Accumulator
A
M
A
A
A
A
A
A
B
B
B
B
B
18
0
LDAB (opr)
Load
Accumulator
B
M
B
18
0
LDD (opr)
Load Double
Accumulator
D
M
A,M + 1
B
18
0
LDS (opr)
Load Stack
Pointer
M : M + 1
SP
18
0
LDX (opr)
Load Index
Register
X
M : M + 1
IX
CD
18
18
18
1A
18
0
LDY (opr)
Load Index
Register
Y
M : M + 1
IY
0
LSL (opr)
Logical Shift
Left
18
LSLA
Logical Shift
Left A
A
LSLB
Logical Shift
Left B
B
INH
58
2
LSLD
Logical Shift
Left Double
INH
05
3
LSR (opr)
Logical Shift
Right
EXT
IND,X
IND,Y
INH
74
64
64
44
18
hh ll
ff
ff
6
6
7
2
0
LSRA
Logical Shift
Right A
A
0
LSRB
Logical Shift
Right B
B
INH
54
2
0
LSRD
Logical Shift
Right Double
INH
04
3
0
MUL
Multiply 8 by 8
Two’s
Complement
Memory Byte
Two’s
Complement
A
Two’s
Complement
B
No operation
OR
Accumulator
A (Inclusive)
A
B
D
0 – M
M
INH
EXT
IND,X
IND,Y
INH
3D
70
60
60
40
10
6
6
7
2
NEG (opr)
18
hh ll
ff
ff
NEGA
0 – A
A
A
NEGB
0 – B
B
B
INH
50
2
NOP
No Operation
A + M
A
INH
IMM
DIR
EXT
IND,X
IND,Y
01
8A
9A
BA
AA
AA
2
2
3
4
4
5
0
ORAA (opr)
A
A
A
A
A
18
ii
dd
hh ll
ff
ff
Table 8 M68HC11 Instruction Set (Sheet 4 of 6)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
A
B
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
A
B
b7
b0
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