參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 14/52頁(yè)
文件大?。?/td> 358K
代理商： M68HC16
MOTOROLA
14
AN1283/D
is added to the value contained in an index register and its extension field. For 16-bit modes, a 16-bit signed
offset contained in the instruction is added to the value contained in an index register and its extension field.
For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the value contained in an
index register. These modes are used for JMP and JSR instructions only.
3.5.4 Inherent Addressing Mode
Inherent mode instructions use information directly available to the processor to determine the effective ad-
dress. Operands (if any) are system resources and are thus not fetched from memory.
3.5.5 Accumulator Offset Addressing Mode
Accumulator offset modes form an effective address by sign-extending the content of accumulator E to 20
bits, then adding the result to an index register and its associated extension field. This mode allows use of
an index register and an accumulator within a loop without corrupting accumulator D.
3.5.6 Relative Addressing Modes
Relative modes are used for branch and long branch instructions. If a branch condition is satisfied, a byte
or word signed two's-complement offset is added to the concatenated PK field and program counter. The
new PK : PC value is the effective address.
3.5.7 Post-Modified Index Addressing Mode
Post-modified index mode is used by the MOVB and MOVW instructions. A signed 8-bit offset is added to
index register X after the effective address formed by XK
:
IX is used.
3.6 Instructions
The instruction set is based upon that of the M68HC11 CPU, but the opcode map has been rearranged to
maximize performance with a 16-bit data bus. Much M68HC11 code can run on the CPU16 following reas-
sembly. The user must take into account changed instruction times, the interrupt mask, and the new inter-
rupt stack frame.
CPU16 instructions consist of an 8-bit opcode, which may be preceded by an 8-bit prebyte and followed by
one or more operands.
Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone, but Page 1, 2, and 3 op-
codes are pointed to by a prebyte code on Page 0. The prebytes are $17 (Page 1), $27 (Page 2), and $37
(Page 3).
Operands can be 4 bits, 8 bits or 16 bits in length. However, because the CPU16 fetches 16-bit instruction
words from even byte boundaries, each instruction must contain an even number of bytes.
Operands are organized as bytes, words, or a combination of bytes and words. Four-bit operands are either
zero-extended to 8 bits, or packed two to a byte. The largest instructions are six bytes in length. Size, order,
and function of operands are evaluated when an instruction is decoded.
A Page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions that use 8-bit indexed,
immediate, and relative addressing modes have this form. Code written with these instructions is very com-
pact.
3.7 CPU16 Pipeline Mechanism
This description is a simplified model of the mechanism the CPU16 uses to fetch and execute instructions.
Functional divisions in the model do not necessarily correspond to distinct architectural subunits of the mi-
croprocessor.
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