參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 358K
代理商： M68HC16
MOTOROLA
16
AN1283/D
Short branch instructions consist of an 8-bit opcode and an 8-bit operand contained in one word. Long
branch instructions consist of an 8-bit prebyte and an 8-bit opcode in one word, followed by an operand
word. Bit condition branches consist of an 8-bit opcode and an 8-bit operand in one word, followed by one
or two operand words.
When a branch instruction executes, PK : PC point to an address equal to the address of the first word of
the instruction plus $0006. The range of displacement for each type of branch is relative to this value. In
addition, because prefetches are automatically aligned to word boundaries, only even offsets are valid. An
odd offset value is rounded down.
3.9.3 Subroutines
Subroutines can be called by short (BSR) or long (LBSR) branches, or by a jump (JSR). The RTS instruction
returns control to the calling routine. BSR consists of an 8-bit opcode with an 8-bit operand. LBSR consists
of an 8-bit prebyte and an 8-bit opcode in one word, followed by an operand word. JSR consists of an 8-bit
opcode with a 20-bit argument. RTS consists of an 8-bit prebyte and an 8-bit opcode in one word.
When a subroutine instruction is executed, PK : PC contain the address of the calling instruction plus $0006.
All three calling instructions stack return PK : PC values prior to processing instructions from the new in-
struction stream. In order for RTS to work with all three calling instructions, however, the value stacked by
BSR must be adjusted.
LBSR and JSR are two-word instructions. In order for program execution to resume with the instruction im-
mediately following them, RTS must subtract $0002 from the stacked PK : PC value. BSR is a one-word
instruction — it subtracts $0002 from PK : PC prior to stacking so that execution will resume correctly.
3.10 Exceptions
An exception is an event that preempts normal instruction process. Exception processing makes the tran-
sition from normal instruction execution to execution of a routine that deals with an exception.
Each exception has an assigned vector that points to an associated handler routine. Exception processing
includes all operations required to transfer control to a handler routine, but does not include execution of
the handler routine itself. Keep the distinction between exception processing and execution of an exception
handler in mind while reading this section.
3.10.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. Exception vectors are contained
in a data structure called the exception vector table, which is located in the first 512 bytes of Bank 0.
All vectors except the reset vector consist of one word and reside in data space. The reset vector consists
of four words that reside in program space. There are 52 predefined or reserved vectors, and 200 user-de-
fined vectors.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are generated by external
devices; others are supplied by the processor. There is a direct mapping of vector number to vector table
address. The processor left shifts the vector number one place (multiplies by two) to convert it to an address.
Table 6
shows the exception vectors.
3.10.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are stacked
at a location pointed to by SK : SP. Unless it is altered during exception processing, the stacked PK : PC
value is the address of the next instruction in the current instruction stream, plus $0006.
the exception stack frame.
Figure 5
shows
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