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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 5/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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AN1283/D
MOTOROLA
5
2.7 Changes in Program Flow
M68HC11 jump, branch, and subroutine instructions initiate changes in program flow. When program flow
changes, instructions are fetched from a new address. When a change in flow is temporary, a return ad-
dress is stored, so that execution of the original instruction stream can resume after the change in flow.
The jump (JMP) instruction uses direct, extended and indexed addressing modes. Jumps are unconditional
changes in flow. No return PC value is stacked prior to executing a jump instruction.
The M68HC11 CPU supports a number of 8-bit relative displacement branch instructions, as well as spe-
cialized bit condition branches that use the direct and indexed addressing modes. Branch instructions are
conditional changes in flow. A change occurs only if a pre-defined condition is satisfied. No return PC value
is stacked prior to executing a branch instruction.
Subroutines are called by special branch (BSR) or jump (JSR) instructions. The RTS instruction returns con-
trol to the calling routine after a subroutine has executed. JSR uses the direct, indexed, and extended ad-
dressing modes; BSR uses only relative addressing mode. When a subroutine instruction is executed, the
PC points to the address of the instruction that follows the instruction that calls the subroutine. Both calling
instructions stack the high and low bytes of this return PC value. The return PC is pulled from the stack when
RTS is executed at the end of a subroutine.
2.8 Reset And Interrupt Vectors
Reset and interrupt operations load the M68HC11 CPU program counter with a vector that points to a new
location from which instructions are to be fetched.
M68HC11 device.
Table 2
shows vector assignments for a typical
2.9 Resets
Resets are generally used to initialize the MCU or to recover from catastrophic failure. A reset immediately
stops program execution and forces the program counter to a known starting address. Internal registers and
control bits are initialized so the MCU can resume operation in a known state. There are four possible sourc-
es of reset. External reset and power-on reset share a vector. The computer operating properly system and
the clock monitor each have a vector.
The M68HC11 CPU distinguishes between internal and external reset conditions by measuring the time it
takes the MCU RESET line to return to logic level one after assertion. When a reset condition is sensed, an
internal circuit drives the RESET pin low for four ECLK cycles, then releases it. Two ECLK cycles later, the
logic level of the RESET line is sampled. If it is still low, the CPU assumes that an external reset has oc-
curred. If it is high, the CPU assumes that reset was initiated internally.
A positive transition on V
clock cycle
delay after the oscillator becomes active allows the clock generator to stabilize. If RESET is low
at the end of 4064 clock cycles, the CPU remains in reset condition until RESET goes high.
dd
generates a power-on reset, which is used only for power-up conditions. A 4064
The MCU includes a computer operating properly (COP) system to help protect against software failures.
When the system is enabled, software is responsible for keeping a free-running watchdog timer from timing
out. If the software fails to update the timer control register, a system reset occurs.
The clock monitor circuit is based on an internal RC time delay. If no MCU clock edges are detected within
the delay period, the clock monitor can generate a system reset.
When a reset condition is recognized, the internal registers and control bits are forced to an initial state.
Depending on the cause of the reset and the operating mode, the reset vector can be fetched from one of
the six possible locations shown in
Table 3
.
The M68HC11 CPU fetches the appropriate vector during the first three cycles after reset, then begins fetch-
ing instructions from the address pointed to by the vector. The stack pointer and other CPU registers are
indeterminate immediately after reset, but the X and I interrupt mask bits in the CCR are set to mask inter-
rupt requests.
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