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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 4/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
4
AN1283/D
2.4.1 Direct Mode
In the direct addressing mode, the low-order byte of the operand address is contained in a single byte fol-
lowing the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00–$FF are
thus accessed directly, using two-byte instructions. Execution time is reduced by eliminating the additional
memory access required for the high-order address byte. In most applications, this 256-byte area is re-
served for frequently referenced data. M68HC11 memory can be configured so that combinations of internal
registers, RAM or external memory occupy these addresses.
2.4.2 Extended Mode
In the extended addressing mode, the effective address of the argument is contained in two bytes following
the opcode byte.
2.4.3 Immediate Mode
In the immediate addressing mode an argument is contained in the byte(s) immediately following the op-
code. The number of bytes following the opcode matches the size of the register or memory location being
operated on. The effective address is the address of the byte following the instruction.
2.4.4 Indexed Modes
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in an index register (IX or IY) — the sum is the effective address. This addressing mode allows
referencing any memory location in the 64 Kbyte address space.
2.4.5 Inherent Modes
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the
opcode. Operations that use only the index registers or accumulators, as well as control instructions with
no arguments, are included in this addressing mode.
2.4.6 Relative Mode
The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit
signed offset included in the instruction is added to the contents of the program counter to form the effective
branch address. Otherwise, control proceeds to the next instruction.
2.5 Instructions
The M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction
and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with
a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restrict-
ed to the number able to be expressed in 8-bit binary numbers.
A four-page opcode map has been implemented to expand the number of instructions. An additional byte,
called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. As
its name implies, the additional byte precedes the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. The
operands contain information the CPU needs for executing the instruction. Complete instructions can be
from one to five bytes long.
2.6 Instruction Execution
The M68HC11 CPU fetches and executes instruction bytes sequentially from byte addresses. The program
counter is incremented by one after each opcode or operand byte fetch.
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