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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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AN1283/D
MOTOROLA
21
Each module that can make an interrupt service request, including the SIM, has an IARB field in its config-
uration register. An IARB field can be assigned a value from %0001 (lowest priority) to %1111 (highest pri-
ority). A value of %0000 in an IARB field causes the CPU16 to process a spurious interrupt exception when
an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SIM IARB value is used for arbitration between
internal and external interrupt requests. The reset value of IARB for the SIM is %1111, and the reset IARB
value for all other modules is %0000. Initialization software must assign different IARB values in order to
implement an arbitration scheme.
Each module must be assigned a unique IARB value. When two or more IARB fields have the same nonzero
value, the CPU16 attempts to interpret multiple vector numbers simultaneously, with unpredictable conse-
quences.
Arbitration must always take place, even when a single source requests service. This point is important for
two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus unless the SIM wins
contention, and failure to contend causes an interrupt acknowledge bus cycle to be terminated by a bus er-
ror, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the data bus
and terminate the bus cycle. In the case of an external interrupt request, because the interrupt acknowledge
cycle is transferred to the external bus, an external device must decode the mask value and respond with
a vector number, then generate bus cycle termination signals. If the device does not respond in time, a spu-
rious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority at
predetermined intervals. By hardware convention, PIT interrupts are serviced before external interrupt ser-
vice requests of the same priority.
3.13.2 Interrupt Processing Summary
A valid interrupt service request has been detected and is pending.
The CPU finishes higher priority exception processing or reaches an instruction boundary.
Processor state is stacked, then the CCR PK extension field is cleared.
FC[2:0] are driven to %111 (CPU space) encoding.
The address bus is driven as follows:
ADDR[23:20] = %1111;
ADDR[19:16] = %1111, indicating an interrupt acknowledge CPU space cycle;
ADDR[15:4] = %111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged;
ADDR0 = %1.
Request priority is latched into the CCR IP field from the address bus.
Modules or external peripherals that have requested interrupt service decode ADDR[3:1].
IARB contention takes place.
The interrupt vector number is generated, in one of four ways:
If contention has not produced a dominant interrupt source (IARB = %0000), the CPU16
generates the spurious interrupt vector number.
If contention has produced a dominant interrupt source, it supplies the vector number.
If the autovector signal is asserted, the CPU16 generates a vector number that corresponds to
interrupt request priority.
If the bus monitor asserts the bus error signal, the CPU16 generates the spurious interrupt vector
number.
The CPU16 converts the vector number to a vector address.
The content of the vector address is loaded into the PC.
The exception handler routine begins to execute.
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