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參數(shù)資料
| 型號： | M68HC16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Microcontroller(16位微控制器) |
| 中文描述： | 16位微控制器（16位微控制器） |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 358K |
| 代理商： | M68HC16 |
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MOTOROLA
20
AN1283/D
3.13 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit, the sys-
tem integration module, and a device or module requesting interrupt service.
The CPU16 provides for eight levels of interrupt priority (0–7), seven automatic interrupt vectors, and 200
assignable interrupt vectors. All interrupts with priorities less than 7 can be masked by the interrupt priority
(IP) field in the condition code register. The CPU16 handles interrupts as a type of asynchronous exception.
Interrupt recognition is based on the states of interrupt request signals IRQ[7:1] and the IP mask value. Each
of the signals corresponds to an interrupt priority. IRQ1 has the lowest priority, and IRQ7 has the highest
priority.
The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.
Masks prevent an interrupt request of a priority less than or equal to the mask value (except for IRQ7) from
being recognized and processed. When IP contains %000, no interrupt is masked. During exception pro-
cessing, the IP field is set to the priority of the interrupt being serviced.
Interrupt request signals can be asserted by external devices or by microcontroller modules. Request lines
are connected internally by means of a wired NOR — simultaneous requests of differing priority can be
made. Internal assertion of an interrupt request signal does not affect the logic state of the corresponding
MCU pin.
External interrupt requests are routed to the CPU16 via the external bus interface and SIM interrupt control
logic. The CPU treats external interrupt requests as though they come from the SIM.
External IRQ[6:1] are active-low level-sensitive inputs. External IRQ7 is an active-low transition-sensitive
input. IRQ7 requires both an edge and a voltage level for validity.
IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent re-
dundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is asserted,
and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted.
Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input cir-
cuitry has hysteresis. To be valid, a request signal must be asserted for at least two consecutive clock pe-
riods. Valid requests do not cause immediate exception processing, but are left pending. Pending requests
are processed at instruction boundaries or when exception processing of higher-priority exceptions is com-
plete.
The CPU16 does not latch the priority of a pending interrupt request. If an interrupt source of higher priority
makes a service request while a lower priority request is pending, the higher priority request is serviced. If
an interrupt request of equal or lower priority than the current IP mask value is made, the CPU does not
recognize the occurrence of the request in any way.
3.13.1 Interrupt Acknowledge and Arbitration
Interrupt acknowledge bus cycles are generated during exception processing. When the CPU16 detects
one or more interrupt requests of a priority higher than the interrupt priority mask value, it performs a CPU
space read from address $FFFFF : [IP] : 1.
The CPU space read cycle performs two functions: it places a mask value corresponding to the highest pri-
ority interrupt request on the address bus, and it acquires an exception vector number from the interrupt
source. The mask value also serves two purposes: it is latched into the CCR IP field in order to mask lower-
priority interrupts during exception processing, and it is decoded by modules that have requested interrupt
service to determine whether the current interrupt acknowledge cycle pertains to them.
Modules that have requested interrupt service decode the IP value placed on the address bus at the begin-
ning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond to the
cycle. Arbitration between simultaneous requests of the same priority is performed by means of serial con-
tention between module interrupt arbitration (IARB) field bit values.
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