參數(shù)資料
型號： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁數(shù)： 13/52頁
文件大?。?/td> 358K
代理商： M68HC16
AN1283/D
MOTOROLA
13
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an operand or an ex-
tension field to form a 20-bit effective address. Bank switching is transparent to most instructions. AD-
DR[19:16] of the effective address are changed to make an access across a bank boundary. However,
extension field values do not change as a result of effective address computation.
3.5.1 Immediate Addressing Modes
In the immediate modes, an argument is contained in a byte or word immediately following the instruction.
For IMM8 and IMM16 modes, the effective address is the address of the argument.
There are three specialized forms of IMM8 addressing. The AIS, AIX/Y/Z, ADDD and ADDE instructions
decrease execution time by sign-extending the 8-bit immediate operand to 16 bits, then adding it to an ap-
propriate register. The MAC and RMAC instructions use an 8-bit immediate operand to specify two signed
4-bit index register offsets. The PSHM and PULM instructions use an 8-bit immediate mask operand to in-
dicate which registers must be pushed to or pulled from the stack.
3.5.2 Extended Addressing Modes
Regular extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective
address is formed by concatenating the EK field and the 16-bit byte address. EXT20 mode is used only by
the JMP and JSR instructions. These instructions contain a 20-bit effective address that is zero-extended
to 24 bits to give the instruction an even number of bytes.
3.5.3 Indexed Addressing Modes
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used to
calculate the effective address. For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction
Table 5 CPU16 Addressing Modes
Mode
Mnemonic
E,X
E,Y
E,Z
EXT
EXT20
IMM8
IMM16
IND8, X
IND8, Y
IND8, Z
IND16, X
IND16, Y
IND16, Z
IND20, X
IND20, Y
IND20, Z
INH
Description
Accumulator Offset
Index Register X with Accumulator E offset
Index Register Y with Accumulator E offset
Index Register Z with Accumulator E offset
Extended
20-bit Extended
8-bit Immediate
16-bit Immediate
Index Register X with unsigned 8-bit offset
Index Register Y with unsigned 8-bit offset
Index Register Z with unsigned 8-bit offset
Index Register X with signed 16-bit offset
Index Register Y with signed 16-bit offset
Index Register Z with signed 16-bit offset
Index Register X with signed 20-bit offset
Index Register Y with signed 20-bit offset
Index Register Z with signed 20-bit offset
Inherent
Signed 8-bit offset added to Index Register X
after effective address is used
8-bit relative
16-bit relative
Extended
Immediate
Indexed 8-Bit
Indexed 16-Bit
Indexed 20-Bit
Inherent
Post-Modified Index
IXP
Relative
REL8
REL16
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