參數(shù)資料
型號(hào)： M68HC16
廠商： Motorola, Inc.
英文描述： 16-Bit Microcontroller(16位微控制器)
中文描述： 16位微控制器（16位微控制器）
文件頁(yè)數(shù)： 32/52頁(yè)
文件大小： 358K
代理商： M68HC16
MOTOROLA
32
AN1283/D
BHI (rel)
Branch if
Higher
Branch if
Higher or
Same
Bit(s) Test A
with Memory
C + Z = 0
REL
22
rr
3
—
—
—
—
—
—
—
—
BHS (rel)
C = 0
REL
24
rr
3
—
—
—
—
—
—
—
—
BITA (opr)
A M
A
A
A
A
A
B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
85
95
B5
A5
A5
C5
D5
F5
E5
E5
2F
18
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
2
3
4
4
5
2
3
4
4
5
3
—
—
—
—
0
—
BITB (opr)
Bit(s) Test B
with Memory
B M
18
—
—
—
—
0
—
BLE (rel)
Branch if
Zero
Branch if
Lower
Branch if
Lower or
Same
Branch if <
Zero
Branch if
Minus
Branch if not
= Zero
Branch if Plus
Branch Always
Branch if
Bit(s) Clear
Z + (N
⊕
V) = 1
—
—
—
—
—
—
—
—
BLO (rel)
C = 1
REL
25
rr
3
—
—
—
—
—
—
—
—
BLS (rel)
C + Z = 1
REL
23
rr
3
—
—
—
—
—
—
—
—
BLT (rel)
N
⊕
V = 1
REL
2D
rr
3
—
—
—
—
—
—
—
—
BMI (rel)
N = 1
REL
2B
rr
3
—
—
—
—
—
—
—
—
BNE (rel)
Z = 0
REL
26
rr
3
—
—
—
—
—
—
—
—
BPL (rel)
BRA (rel)
BRCLR(opr)
N = 0
1 = 1
M mm = 0
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
2A
20
13
1F
1F
21
12
1E
1E
14
1C
1C
8D
rr
rr
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
3
3
6
7
8
3
6
7
8
6
7
8
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(msk)
(rel)
18
BRN (rel)
BRSET(opr)
Branch Never
Branch if
Bit(s) Set
1 = 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(msk)
(rel)
(M) mm = 0
18
BSET (opr)
(msk)
Set Bit(s)
M + mm
M
18
—
—
—
—
0
—
BSR (rel)
Branch to
Subroutine
Branch if
Overflow Clear
Branch if
Overflow Set
Compare A to
B
Clear Carry Bit
Clear
Interrupt Mask
Clear Memory
Byte
See Figure 3–2
—
—
—
—
—
—
—
—
BVC (rel)
V = 0
REL
28
rr
3
—
—
—
—
—
—
—
—
BVS (rel)
V = 1
REL
29
rr
3
—
—
—
—
—
—
—
—
CBA
A – B
INH
11
—
2
—
—
—
—
CLC
CLI
0
C
0
I
INH
INH
0C
0E
—
—
2
2
—
—
—
—
—
—
—
0
—
—
—
—
—
—
0
—
CLR (opr)
0
M
EXT
IND,X
IND,Y
INH
7F
6F
6F
4F
18
hh ll
ff
ff
6
6
7
2
—
—
—
—
0
1
0
0
CLRA
Clear
Accumulator A
Clear
Accumulator B
Clear
Overflow Flag
Compare A to
Memory
0
A
A
—
—
—
—
—
0
1
0
0
CLRB
0
B
B
INH
5F
—
2
—
—
—
—
0
1
0
0
CLV
0
V
INH
0A
—
2
—
—
—
—
—
—
0
—
CMPA (opr)
A – M
A
A
A
A
A
B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
81
91
B1
A1
A1
C1
D1
F1
E1
E1
73
63
63
18
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
2
3
4
4
5
2
3
4
4
5
6
6
7
—
—
—
—
CMPB (opr)
Compare B to
Memory
B – M
18
—
—
—
—
COM (opr)
Ones
Complement
Memory Byte
$FF – M
M
18
—
—
—
—
0
1
Table 8 M68HC11 Instruction Set (Sheet 2 of 6)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
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