
MOTOROLA
40
AN1283/D
BCS4
BEQ4
BGE4
Branch if Carry Set
If C = 1, branch
REL8
B5
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Equal
If Z = 1, branch
REL8
B7
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Greater Than
or Equal to Zero
Enter Background De-
bug Mode
If N
⊕
V = 0, branch
REL8
BC
rr
6, 2
—
—
—
—
—
—
—
—
BGND
If BDM enabled
enter BDM;
else, illegal instruction
If Z + (N
⊕
V) = 0, branch
INH
37A6
—
—
—
—
—
—
—
—
—
—
BGT 4
Branch if Greater Than
Zero
Branch if Higher
REL8
BE
rr
6, 2
—
—
—
—
—
—
—
—
BHI 4
BITA
If C + Z = 0, branch
REL8
B2
rr
6, 2
—
—
—
—
—
—
—
—
Bit Test A
(A) (M)
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
IND8, X
IND8, Y
IND8, Z
IMM8
IND16, X
IND16, Y
IND16, Z
EXT
E, X
E, Y
E, Z
REL8
49
59
69
79
1749
1759
1769
1779
2749
2759
2769
C9
D9
E9
F9
17C9
17D9
17E9
17F9
27C9
27D9
27E9
BF
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
ff
ff
ff
ii
gggg
gggg
gggg
hh ll
—
—
—
rr
6
6
6
2
6
6
6
6
6
6
6
6
6
6
2
6
6
6
6
6
6
6
—
—
—
—
0
—
BITB
Bit Test B
(B) (M)
—
—
—
—
0
—
BLE 4
Branch if Less Than or
Equal to Zero
Branch if Lower or
Same
Branch if Less Than
Zero
Branch if Minus
If Z + (N
⊕
V) = 1, branch
6, 2
—
—
—
—
—
—
—
—
BLS4
If C + Z = 1, branch
REL8
B3
rr
6, 2
—
—
—
—
—
—
—
—
BLT4
If N
⊕
V = 1, branch
REL8
BD
rr
6, 2
—
—
—
—
—
—
—
—
BMI 4
BNE 4
BPL4
BRA
BRCLR4
If N = 1, branch
REL8
BB
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Not Equal
If Z = 0, branch
REL8
B6
rr
6, 2
—
—
—
—
—
—
—
—
Branch if Plus
If N = 0, branch
REL8
BA
rr
6, 2
—
—
—
—
—
—
—
—
Branch Always
Branch if Bit(s) Clear
If 1 = 1, branch
If (M) (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B0
CB
DB
EB
0A
rr
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Y
IND16, Z
EXT
1A
2A
3A
mm ff rr
mm ff rr
mm ff rr
mm
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
rr
mm ff rr
mm ff rr
mm ff rr
mm
gggg rrrr
mm
gggg rrrr
mm
gggg rrrr
mm hh ll
rrrr
mm gggg
mm gggg
mm gggg
mm hh ll
mm ff
mm ff
mm ff
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
BRN
BRSET4
Branch Never
Branch if Bit(s) Set
If 1 = 0, branch
If (M) (Mask) = 0, branch
REL8
IND8, X
IND8, Y
IND8, Z
IND16, X
B1
8B
9B
AB
0B
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IND16, Y
IND16, Z
EXT
1B
2B
3B
10, 12
10, 12
10, 12
10, 14
10, 14
10, 14
10, 14
BSET
Set Bit(s)
(M) (Mask)
M
IND16, X
IND16, Y
IND16, Z
EXT
IND8, X
IND8, Y
IND8, Z
09
19
29
39
1709
1719
1729
8
8
8
8
8
8
8
—
—
—
—
0
—
Table 9 CPU16 Instruction Set Summary (Sheet 4 of 15)
Mnemonic
Operation
Description
Address
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S MV H
EV
N
Z
V
C