參數(shù)資料
型號(hào)： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 98/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
98 of 169
9.5.5 Receive Serial Interface
Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that
throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet
processor block has seventeen registers.
9.5.5.1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Register Bit Descriptions
LI.RSLCR
Receive Serial Interface Configuration Register
100h
7
-
0
6
-
0
5
-
0
4
-
0
3
-
0
2
-
0
1
-
0
0
RDENPLT
0
Bit 0: Receive Data Enable Polarity (RDENPLT)
Receive Data Enable Polarity. If set to 1, RDEN Low enables
reception of the bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.RPPCL
Receive Packet Processor Control Low Register
101h
7
-
0
6
-
0
5
4
3
2
1
0
RFPD
0
RF16
0
RFED
0
RDD
0
RBRE
0
RCCE
0
Bit 5: Receive FCS Processing Disable (RFPD)
– When equal to 0, FCS processing is performed and FCS is
appended to packets. When set to 1, FCS processing is disabled (the packets do not have an FCS appended). In
X.86 mode, FCS processing is always enabled.
Bit 4: Receive FCS-16 Enable (RF16)
– When 0, the error checking circuit uses a 32-bit FCS. When 1, the error
checking circuit uses a 16-bit FCS. This bit is ignored when FCS processing is disabled. In X.86 mode, the FCS is
always 32 bits.
Bit 3: Receive FCS Extraction Disable (RFED)
– When 0, the FCS bytes are discarded. When 1, the FCS bytes
are passed on. This bit is ignored when FCS processing is disabled. In X.86 mode, FCS bytes are discarded.
Bit 2: Receive Descrambling Disable (RDD)
– When equal to 0, X
43
+1 descrambling is performed. When set to
1, descrambling is disabled.
Bit 1: Receive Bit Reordering Enable (RBRE)
– When equal to 0, reordering is disabled and the first bit received
is expected to be the MSB DT [7] of the byte. When set to 1, bit reordering is enabled and the first bit received is
expected to be the LSB DT [0] of the byte. Note that function is controlled by the BREO in Hardware Mode.
Bit 0: Receive Clear Channel Enable (RCCE)
– When equal to 0, packet processing is enabled. When set to 1,
the device is in clear channel mode and all packet-processing functions except descrambling and bit reordering
are disabled.
相關(guān)PDF資料
PDF描述
DS3803 1024K Flexible NV SRAM SIMM(1024K靈活的非易失性SRAM SIMM)
DS3903E-020 Triple 128-Position Nonvolatile Digital Potentiometer
DS3994 4-Channel Cold-Cathode Fluorescent Lamp Controller
DS4077 77.76MHz VCXO
DS4077L-0C0 77.76MHz VCXO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS33ZH11+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10/100 ENETXPORT HMODE MAP IND RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS34 制造商:LUMILEDS 制造商全稱:LUMILEDS 功能描述:power light source Luxeon V Emitter
DS-3400D UK 制造商:TRUST 功能描述:DESKTOP WIRELESS OPTICAL TRUST
DS3404FP000 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,3P480V
DS3404FP000/JG63 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,404,3P480V,JG63,SC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*