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| 型號(hào)： | DS33ZH11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100 |
| 文件頁(yè)數(shù)： | 5/169頁(yè) |
| 文件大?。?/td> | 1049K |
| 代理商： | DS33ZH11 |
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DS33Z11 Ethernet Mapper
5 of 169
LIST OF FIGURES
Figure 3-1 Ethernet to WAN Extension (No Framing)..............................................................................................11
Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) ............................................................................12
Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing....................................................................................12
Figure 3-4 Ethernet over DSL...................................................................................................................................13
Figure 3-5 Copper to Fiber Connection ....................................................................................................................13
Figure 6-1 Detailed Block Diagram...........................................................................................................................16
Figure 7-1 DS33Z11 169-Ball CSBGA Pinout ..........................................................................................................27
Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only) .......................................................28
Figure 8-1 Clocking for the DS33Z11.......................................................................................................................32
Figure 8-2 Device Interrupt Information Flow Diagram.............................................................................................37
Figure 8-3 Flow Control Using Pause Control Frame...............................................................................................42
Figure 8-4 IEEE 802.3 Ethernet Frame....................................................................................................................43
Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode............................................................45
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode ..........................................................................................46
Figure 8-7 RMII Interface..........................................................................................................................................48
Figure 8-8 MII Management Frame..........................................................................................................................49
Figure 8-9 PRBS Synchronization State Diagram ....................................................................................................51
Figure 8-10 Repetitive Pattern Synchronization State Diagram ...............................................................................52
Figure 8-11 LAPS Encoding of MAC Frames Concept.............................................................................................56
Figure 8-12 X.86 Encapsulation of the MAC field.....................................................................................................57
Figure 8-13 CIR in the WAN Transmit Path .............................................................................................................60
Figure 10-1 TX Serial Interface Functional Timing.................................................................................................139
Figure 10-2 RX Serial Interface Functional Timing.................................................................................................139
Figure 10-3 Transmit Byte Sync Functional timing.................................................................................................140
Figure 10-4 Receive Byte Sync Functional Timing.................................................................................................140
Figure 10-5 MII Transmit Functional Timing...........................................................................................................141
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing ..............................................................141
Figure 10-7 MII Receive Functional Timing............................................................................................................141
Figure 10-8 RMII Transmit Interface Functional Timing.........................................................................................141
Figure 10-9 RMII Receive Interface Functional Timing ..........................................................................................142
Figure 10-10 SPI Master Functional Timing...........................................................................................................142
Figure 11-1 Transmit MII Interface .........................................................................................................................146
Figure 11-2 Receive MII Interface Timing...............................................................................................................147
Figure 11-3 Transmit RMII Interface.......................................................................................................................148
Figure 11-4 Receive RMII Interface Timing............................................................................................................149
Figure 11-5 MDIO Timing.......................................................................................................................................150
Figure 11-6 Transmit WAN Timing.........................................................................................................................151
Figure 11-7 Receive WAN timing ...........................................................................................................................152
Figure 11-8 SDRAM Interface Timing.....................................................................................................................154
Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00).......................................................................156
Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00).....................................................................156
Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01)..............................................................157
Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01)..............................................................157
Figure 11-13 EEPROM Interface Timing................................................................................................................158
Figure 11-14 JTAG Interface Timing Diagram........................................................................................................159
Figure 12-1 JTAG Functional Block Diagram.........................................................................................................160
Figure 12-2 TAP Controller State Diagram.............................................................................................................163
Figure 12-3 JTAG Functional Timing......................................................................................................................166
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS33ZH11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10/100 ENETXPORT HMODE MAP IND RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34 | 制造商:LUMILEDS 制造商全稱:LUMILEDS 功能描述:power light source Luxeon V Emitter |
| DS-3400D UK | 制造商:TRUST 功能描述:DESKTOP WIRELESS OPTICAL TRUST |
| DS3404FP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,3P480V |
| DS3404FP000/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,404,3P480V,JG63,SC |
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