參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 1/169頁
文件大小： 1049K
代理商： DS33ZH11
1 of 169
REV: 021805
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata
.
GENERAL DESCRIPTION
The DS33Z11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a PDH/TDM data
stream. The serial link supports bidirectional-
synchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed
Information
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z11 can
operate with an inexpensive external processor,
EEPROM or in a stand-alone hardware mode.
Rate
(CIR)
controller
FUNCTIONAL DIAGRAM
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and RMII)
Half/Full Duplex with Automatic Flow Control
52Mbps Synchronous TDM Serial Port with
Independent Transmit and Receive Timing
HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill
Committed Information Rate Controller Provides
Fractional Allocations in 512kbps Increments
Programmable BERT for Serial (TDM) Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
SPI Interface and Hardware Mode for Operation
Without a Host Processor
Also Available in a 100-Ball, 10mm CSBGA—the
Hardware/SPI Mode-Only DS33ZH11
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support
Feature Highlights continued on page
.
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