參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 24/169頁
文件大小： 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
24 of 169
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
SDRAM CONTROLLER
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDATA[16]
SDATA[17]
SDATA[18]
SDATA[19]
SDATA[20]
SDATA[21]
SDATA[22]
SDATA[23]
SDATA[24]
SDATA[25]
SDATA[26]
SDATA[27]
SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
SDA[0]
M1
L2
N1
M2
N2
N4
N3
L4
J3
M3
H3
J1
J2
K1
K2
L1
M12
H11
M11
N13
N11
L13
N12
K13
J13
J12
H13
H12
G12
F11
G11
L10
N9
H1
F2
J1
D2
K1
K2
J2
C3
D3
E2
C2
F1
G1
D1
D2
E1
K6
G7
J7
K8
K7
J8
H7
K9
J9
H8
H9
C7
G9
G8
G6
C6
J5
IOZ
SDRAM Data Bus (Bits 0 through 31):
The 32 pins of the
SDRAM data bus are inputs for read operations and
outputs for write operations. At all other times, these pins
are high-impedance.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
SDA[1]
N10
K5
SDA[2]
L11
H6
SDA[3]
K11
F9
SDA[4]
L7
C4
SDA[5]
L8
H4
SDA[6]
L9
G5
SDA[7]
L5
G4
SDA[8]
M5
F8
SDA[9]
M7
F5
SDA[10]
M8
H5
SDA[11]
N8
K4
O
SDRAM Address Bus 0 through 11:
The 12 pins of the
SDRAM address bus output the row address first, followed
by the column address. The row address is determined by
SDA0 to SDA11 at the rising edge of clock. Column
address is determined by SDA0-SDA9 and SDA11 at the
rising edge of the clock. SDA10 is used as an auto-
precharge signal.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
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參數(shù)描述
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