參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 23/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
23 of 169
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
MODEC[0]
D6
—
MODEC[1]
D7
A4
I
Mode Control:
Software Mode Options (HWMODE = 0)
00 = Read/Write Strobe Used (Intel Mode)
01 = Data Strobe Used (Motorola Mode)
10 –SPI Master Mode (External EEPROM)
11- Reserved. Do not use.
Hardware Mode Options (HWMODE = 1)
00 = Default Hardware Mode. See
Table 8-8
.
01 = Reserved. Do not use.
10 = Reserved. Do not use.
11 = Reserved. Do not use.
Note that in the 100-pin CSBGA (DS33ZH11) package,
only MODEC[1] is available to the user. MODEC[0] is
internally connected to V
SS
.
DCE or DTE Selection:
The user must set this pin high
for DCE Mode selection or low for DTE Mode. This input
affects operation in both software and hardware mode. In
DCE Mode, the DS33Z11 MAC port can be directly
connected to another MAC. In DCE Mode, the Transmit
clock (TX_CLK) and Receive clock (RX_CLK) are output
by the DS33Z11.
Note that there is no software bit selection of DCEDTES.
Note that DCE Mode is only relevant when the MAC
interface is in MII mode.
DCEDTES
A13
—
I
RMIIMIIS
C4
—
I
RMII or MII Selection:
Set high to configure the MAC for
RMII interfacing. Set low for MII interfacing.
FULLDS
A9
—
I
Full Duplex Selection (Hardware Mode):
When in
Hardware Mode, this pin selects full duplex MAC operation
when set high. If low, the MAC will operate in half duplex
mode. In software mode, this pin has no effect and duplex
selection is controlled in the SU.GCR register.
H10S
B10
—
I
100Mb/10Mb (Hardware Mode):
When in Hardware
Mode, this pin selects the packet PHY data rate. Set high
for 100 Mbps. Set low for the MII/RMII interface to run at
10 Mbps. In the software mode this pin has no effect and
the rate selection is controlled in the
SU.GCR
register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to V
DD
.
Automatic Flow Control (Hardware Mode):
When in
Hardware Mode, set high to enable automatic flow control
pause and backpressure application. In the software mode
this pin has no effect and the rate selection is controlled by
the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to V
DD
.
AFCS
C10
—
I
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