
DS33Z11 Ethernet Mapper
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LIST OF TABLES
Table 2-1 T1-Related Telecommunications Specifications ......................................................................................10
Table 7-1 Detailed Pin Descriptions .........................................................................................................................17
Table 8-1 Clocking Options for the Ethernet Interface .............................................................................................31
Table 8-2 Reset Functions........................................................................................................................................34
Table 8-3 Registers Related to Connections and Queues .......................................................................................39
Table 8-4 Options for Flow Control...........................................................................................................................40
Table 8-5 Registers Related to Setting the Ethernet Port.........................................................................................44
Table 8-6 MAC Control Registers.............................................................................................................................47
Table 8-7 MAC Status Registers..............................................................................................................................47
Table 8-8 Hardware Mode and Typical Applications ................................................................................................61
Table 8-9 Specific Functional Default Values for Hardware Mode...........................................................................62
Table 8-10 Hardware Mode Pins..............................................................................................................................64
Table 9-1 Register Address Map..............................................................................................................................65
Table 9-2 Global Register Bit Map............................................................................................................................66
Table 9-3 Arbiter Register Bit Map ...........................................................................................................................67
Table 9-4 BERT Register Bit Map ............................................................................................................................67
Table 9-5 Serial Interface Register Bit Map..............................................................................................................68
Table 9-6 Ethernet Interface Register Bit Map .........................................................................................................70
Table 9-7 MAC Indirect Register Bit Map .................................................................................................................71
Table 10-1 EEPROM Program Memory Map.........................................................................................................143
Table 10-2 EEPROM Program Sequence and Example for Indirect MAC Registers.............................................143
Table 11-1 Recommended DC Operating Conditions............................................................................................144
Table 11-2 DC Electrical Characteristics................................................................................................................144
Table 11-3 SDRAM Interface Timing......................................................................................................................153
Table 12-1 Instruction Codes for IEEE 1149.1 Architecture...................................................................................164
Table 12-2 ID Code Structure.................................................................................................................................165