參數資料
型號: DS33ZH11
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 網絡接口
英文描述: Ethernet Mapper
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝: 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數: 39/169頁
文件大?。?/td> 1049K
代理商: DS33ZH11
DS33Z11 Ethernet Mapper
It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers
must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data
may be transmitted. The proper procedure for setting up a connection follows:
39 of 169
Set up the queue sizes for both transmit and receive queue (AR.TQSC1 and AR.RQSC1).
Set up the high/low thresholds and interrupt enables if desired (GL.TRQIE, LI.TQTIE, SU.QRIE)
Reset all the pointers for the connection desired (GL.C1QPR)
Set up the connections (GL.CON1)
If a connection is disconnected, reset the queue pointers after the disconnection.
Table 8-3 Registers Related to Connections and Queues
Register
GL.CON1
Enables connection between the Ethernet Interface and the Serial Interface.
Note that once connection is set up, then the queues and thresholds can be
setup for that connection.
AR.TQSC1
Size for the Transmit Queue in Number of 32—2K packets.
AR.RQSC1
Size for the Receive Queue in Number of 32—2K packets.
GL.TRQIE
Interrupt enable for items related to the connections at the global level
GL.TRQIS
Interrupt enable status for items related to the connections at the global level
LI.TQTIE
Enables for the Transmit queue crossing high and low thresholds
LI.TQCTLS
Latched status bits for connection high and low thresholds for the transmit
queue.
SU.QRIE
Enables for the receive queue crossing high and low thresholds
SU.QCRLS
Latched status bits for receive queue high and low thresholds.
GL.C1QPR
Resets the connection pointer.
8.11 Arbiter
The Arbiter manages the transport between the Ethernet port and the Serial port. It is responsible for queuing and
dequeuing packets to a single external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer
data to and from the SDRAM.
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