參數(shù)資料
型號(hào)： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 2/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
2 of 169
TABLE OF CONTENTS
1
DESCRIPTION .............................................................................................................................. 7
2
FEATURE HIGHLIGHTS ............................................................................................................... 8
2.1
G
ENERAL
.......................................................................................................................................................8
2.2
S
ERIAL
I
NTERFACE
.........................................................................................................................................8
2.3
HDLC ...........................................................................................................................................................8
2.4
C
OMMITTED
I
NFORMATION
R
ATE
(CIR) C
ONTROLLER
......................................................................................8
2.5
X.86 S
UPPORT
..............................................................................................................................................8
2.6
SDRAM I
NTERFACE
.......................................................................................................................................9
2.7
MAC I
NTERFACE
............................................................................................................................................9
2.8
M
ICROPROCESSOR
I
NTERFACE
.......................................................................................................................9
2.9
S
ERIAL
SPI I
NTERFACE
—M
ASTER
M
ODE
O
NLY
..............................................................................................9
2.10
D
EFAULT
C
ONFIGURATIONS
............................................................................................................................9
2.11
T
EST AND
D
IAGNOSTICS
.................................................................................................................................9
2.12
S
PECIFICATIONS
C
OMPLIANCE
......................................................................................................................10
APPLICATIONS........................................................................................................................... 11
3
4
ACRONYMS AND GLOSSARY................................................................................................... 14
5
MAJOR OPERATING MODES.................................................................................................... 15
6
BLOCK DIAGRAMS.................................................................................................................... 16
7
PIN DESCRIPTIONS................................................................................................................... 17
7.1
P
IN
F
UNCTIONAL
D
ESCRIPTION
.....................................................................................................................17
FUNCTIONAL DESCRIPTION..................................................................................................... 29
8.1
P
ROCESSOR
I
NTERFACE
...............................................................................................................................29
8.1.1
Read-Write/Data Strobe Modes..........................................................................................................30
8.1.2
Clear on Read.....................................................................................................................................30
8.1.3
Interrupt and Pin Modes......................................................................................................................30
8.2
SPI S
ERIAL
EEPROM I
NTERFACE
................................................................................................................30
8.3
CLOCK STRUCTURE ...............................................................................................................................31
8.3.1
Serial Interface Clock Modes..............................................................................................................33
8.3.2
Ethernet Interface Clock Modes..........................................................................................................33
8.4
R
ESETS
A
ND
L
OW
P
OWER
M
ODES
...............................................................................................................34
8.5
I
NITIALIZATION AND
C
ONFIGURATION
.............................................................................................................35
8.6
G
LOBAL
R
ESOURCES
...................................................................................................................................35
8.7
P
ER
-P
ORT
R
ESOURCES
...............................................................................................................................35
8.8
D
EVICE
I
NTERRUPTS
....................................................................................................................................36
8.9
S
ERIAL
I
NTERFACE
.......................................................................................................................................38
8.10
C
ONNECTIONS AND
Q
UEUES
.........................................................................................................................38
8.11
A
RBITER
......................................................................................................................................................39
8.12
F
LOW
C
ONTROL
...........................................................................................................................................40
8.12.1
Full-Duplex Flow Control.....................................................................................................................41
8.12.2
Half Duplex Flow control.....................................................................................................................42
8.12.3
Host-Managed Flow control................................................................................................................42
8.13
ETHERNET I
NTERFACE
P
ORT
.....................................................................................................................43
8.13.1
DTE and DCE Mode ...........................................................................................................................45
8.14
E
THERNET
MAC ..........................................................................................................................................46
8.14.1
MII Mode Options................................................................................................................................48
8.14.2
RMII Mode...........................................................................................................................................48
8.14.3
PHY MII Management Block and MDIO Interface...............................................................................49
8.15
BERT..........................................................................................................................................................50
8.15.1
Receive Data Interface........................................................................................................................50
8.15.2
Repetitive Pattern Synchronization.....................................................................................................51
8
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