參數(shù)資料
型號(hào)： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 115/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
115 of 169
SU.LPBK
Ethernet Interface Loopback Control Register
14Fh
7
-
0
6
-
0
5
-
0
4
-
0
3
-
0
2
-
0
1
-
0
0
QLP
0
Bit 0: Queue Loopback Enable (QLP)
If this bit is set to 1, data from the Ethernet Interface receive queue is
looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is
removed.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: CRCS
If this bit is zero (default), the received MAC or Ethernet Frame CRC is stripped before the data is
encapsulated and transmitted on the serial interface. Data received from the serial interface is decapsulated, a
CRC is recalculated and appended to the packet for transmission to the Ethernet interface. If this bit is set to 1, the
CRC is not stripped from received packets prior to encapsulation and transmission to the serial interface, and data
received from the serial interface is decapsulated directly. No CRC recalculation is performed on data received
from the serial interface. Note that the maximum packet size supported by the Ethernet interface is still 2016 (this
includes the 4 bytes of CRC).
SU.GCR
Ethernet Interface General Control Register
150h
7
-
0
6
-
0
5
-
0
4
-
0
3
2
1
0
CRCS
0
H10S
0
ATFLOW
1
JAME
0
Bit 2: H10S
If this bit is set the MAC will operate at 100 Mbps. If this bit is zero, the MAC will operate at 10 Mbps.
This bit controls the 10/100 selection for RMII and DCE Mode. In DTE and MII mode, the MAC determines the
data rate from the incoming TX_CLK and RX_CLK.
Bit 1: Automatic Flow Control Enable (ATFLOW)
If this bit is set to 1, automatic flow control is enabled based
on the connection receive queue size and high watermarks. Pause frames are sent automatically in full duplex
mode. The pause time must be programmed through SU.MACFCR. The jam sequence will not be sent
automatically in half duplex mode unless the JAME bit is set. This bit is applicable only in software mode.
Bit 0: Jam Enable (JAME)
If this bit is set to 1, a Jam sequence is sent for a duration of 4 bytes. This function is
only valid in half duplex mode, and will only function if Automatic Flow Control is disabled. Note that if the receive
queue size is less than receive high threshold, setting a JAME will JAM one received frame. If JAME is set and the
receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties
below the threshold.
Note that SU.GCR is only valid in the software mode. In hardware mode, pins are used to control Automatic flow
control and 100/10-speed selection.
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