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參數(shù)資料
| 型號： | DS33ZH11 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Ethernet Mapper |
| 中文描述： | DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100 |
| 文件頁數(shù)： | 161/169頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | DS33ZH11 |
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DS33Z11 Ethernet Mapper
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TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See Figure 12-2 for a diagram of the state machine operation.
Test-Logic-Reset
Upon power-up, the TAP Controller is in the Test-Logic-Reset state. The Instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test
registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the
controller to the Select-IR-Scan state.
Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its
current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go
to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data
one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-
DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with
JTMS HIGH will put the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS33ZH11+ | 功能描述:網(wǎng)絡控制器與處理器 IC 10/100 ENETXPORT HMODE MAP IND RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34 | 制造商:LUMILEDS 制造商全稱:LUMILEDS 功能描述:power light source Luxeon V Emitter |
| DS-3400D UK | 制造商:TRUST 功能描述:DESKTOP WIRELESS OPTICAL TRUST |
| DS3404FP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,3P480V |
| DS3404FP000/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,404,3P480V,JG63,SC |
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