參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 3/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
3 of 169
8.15.3
Pattern Monitoring...............................................................................................................................52
8.15.4
Pattern Generation..............................................................................................................................52
8.16
T
RANSMIT
P
ACKET
P
ROCESSOR
...................................................................................................................53
8.17
R
ECEIVE
P
ACKET
P
ROCESSOR
.....................................................................................................................54
8.18
X.86 E
NCODING AND
D
ECODING
...................................................................................................................56
8.19
C
OMMITTED
I
NFORMATION
R
ATE
C
ONTROLLER
..............................................................................................59
8.20
H
ARDWARE
M
ODE
........................................................................................................................................61
DEVICE REGISTERS.................................................................................................................. 65
9.1
R
EGISTER
B
IT
M
APS
....................................................................................................................................66
9.1.1
Global Register Bit Map ......................................................................................................................66
9.1.2
Arbiter Register Bit Map......................................................................................................................67
9.1.3
BERT Register Bit Map.......................................................................................................................67
9.1.4
Serial Interface Register Bit Map ........................................................................................................68
9.1.5
Ethernet Interface Register Bit Map....................................................................................................70
9.1.6
MAC Register Bit Map.........................................................................................................................71
9.2
G
LOBAL
R
EGISTER
D
EFINITIONS
...................................................................................................................73
9.3
A
RBITER
R
EGISTERS
....................................................................................................................................80
9.3.1
Arbiter Register Bit Descriptions.........................................................................................................80
9.4
BERT R
EGISTERS
.......................................................................................................................................81
9.5
S
ERIAL
I
NTERFACE
R
EGISTERS
.....................................................................................................................88
9.5.1
Serial Interface Transmit and Common Registers..............................................................................88
9.5.2
Serial Interface Transmit Register Bit Descriptions ............................................................................88
9.5.3
Transmit HDLC Processor Registers..................................................................................................89
9.5.4
X.86 Registers.....................................................................................................................................96
9.5.5
Receive Serial Interface......................................................................................................................98
9.6
E
THERNET
I
NTERFACE
R
EGISTERS
.............................................................................................................111
9.6.1
Ethernet Interface Register Bit Descriptions.....................................................................................111
9.6.2
MAC Registers..................................................................................................................................123
10
FUNCTIONAL TIMING .............................................................................................................. 139
10.1
F
UNCTIONAL
S
ERIAL
I/O T
IMING
.................................................................................................................139
10.2
MII
AND
RMII I
NTERFACES
.........................................................................................................................140
10.3
SPI I
NTERFACE
M
ODE AND
EEPROM P
ROGRAM
S
EQUENCE
......................................................................142
11
OPERATING PARAMETERS .................................................................................................... 144
11.1
T
HERMAL
C
HARACTERISTICS
......................................................................................................................145
11.2
T
HETA
-JA
VS
. A
IRFLOW
.............................................................................................................................145
11.3
T
RANSMIT
MII I
NTERFACE
..........................................................................................................................146
11.4
R
ECEIVE
MII I
NTERFACE
............................................................................................................................147
11.5
T
RANSMIT
RMII I
NTERFACE
........................................................................................................................148
11.6
R
ECEIVE
RMII I
NTERFACE
..........................................................................................................................149
11.7
MDIO I
NTERFACE
......................................................................................................................................150
11.8
T
RANSMIT
WAN I
NTERFACE
.......................................................................................................................151
11.9
R
ECEIVE
WAN
I
NTERFACE
.........................................................................................................................152
11.10
SDRAM T
IMING
.........................................................................................................................................153
11.11
AC C
HARACTERISTICS
—M
ICROPROCESSOR
B
US
T
IMING
............................................................................155
11.12
EEPROM I
NTERFACE
T
IMING
....................................................................................................................158
11.13
JTAG I
NTERFACE
T
IMING
...........................................................................................................................159
12
JTAG INFORMATION ............................................................................................................... 160
12.1
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
............................................................................160
12.2
I
NSTRUCTION
R
EGISTER
.............................................................................................................................163
12.2.1
SAMPLE:PRELOAD .........................................................................................................................164
12.2.2
BYPASS............................................................................................................................................164
12.2.3
EXTEST............................................................................................................................................164
12.2.4
CLAMP..............................................................................................................................................164
12.2.5
HIGHZ...............................................................................................................................................164
12.2.6
IDCODE............................................................................................................................................164
9
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