參數(shù)資料
型號： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 20/169頁
文件大小： 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
20 of 169
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
RX_ERR
B12
B9
I
Receive Error (MII):
Asserted by the MAC PHY for one or
more RX_CLK periods indicating that an error has
occurred. Active High indicates Receive code group is
invalid. If CRS_DV is low, RX_ERR has no effect. This is
synchronous with RX_CLK. In DCE mode, this signal must
be grounded.
Receive Error (RMII):
Signal is synchronous to REF_CLK.
COL_DET
B13
—
I
Collision Detect (MII):
Asserted by the MAC PHY to
indicate that a collision is occurring. In DCE Mode this
signal should be connected to ground. This signal is only
valid in half duplex mode, and is ignored in full duplex
mode
Management Data Clock (MII):
Clocks management data
between the PHY and DS33Z11. The clock is derived from
the REF_CLK, with a maximum frequency is 1.67 MHz.
The user must leave this pin unconnected in the DCE
Mode.
MII Management Data IO (MII):
Data path for control
information between the PHY and DS33Z11. When not
used, pull to logic high externally through a 10k resistor.
The MDC and MDIO pins are used to write or read up to
32 Control and Status Registers in 32 PHY Controllers.
This port can also be used to initiate Auto-Negotiation for
the PHY. The user must leave this pin unconnected in the
DCE Mode.
MICRO PORT/SPI
MDC
C12
—
O
MDIO
C13
—
IO
A0/BREO
A1
Potential
future
revision to
add on
ball A5
I
Address Bit 0:
Address bit 0 of the microprocessor
interface. Least Significant Bit
BREO (Hardware Mode):
Used in Hardware Mode to
reverse the ordering of HDLC transmit and receive
functions. Active high input. When 0, the first bit received
is the MSB. When 1, bit the first bit received is the LSB.
The software registers used for control of this function are
LI.RPPCL and LI.TPPCL.
A1/SCD
B1
Potential
future
revision to
add on
ball D8
—
Address Bit 1:
Address bit 1 of the microprocessor
interface.
SCD (Hardware Mode):
Used in Hardware Mode to
disable X
43
+1 bit scrambling for both the transmit and
receive paths. Applies to HDLC and X.86 transport. When
1, X
+1 scrambling is disabled. When 0, X
+1 scrambling
is enabled. The software registers used for control of this
function are LI.RPPCL and LI.TPPCL.
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