參數(shù)資料
型號(hào)： DS33ZH11
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： Ethernet Mapper
中文描述： DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA100
封裝： 10 X 10 MM, 1.41 MM HEIGHT, 0.80 MM PITCH, CSBGA-100
文件頁數(shù)： 26/169頁
文件大?。?/td> 1049K
代理商： DS33ZH11
DS33Z11 Ethernet Mapper
26 of 169
NAME
PIN #
DS33Z11
CSBGA (169)
PIN #
DS33ZH11
BGA(100)
TYPE
FUNCTION
JTAG INTERFACE
Active-Low JTAG Reset:
JTRST
is used to
asynchronously reset the test access port controller. After
power-up, a rising edge on
JTRST
will reset the test port
and cause the device IO enter the JTAG DEVICE ID
mode. Pulling
JTRST
low restores normal device
operation.
JTRST
is pulled HIGH internally via a 10k
resistor operation. If boundary scan is not used, this pin
should be held low.
JTRST
E6
—
Ipu
JTCLK
D4
—
Ipu
JTAG Clock:
This signal is used to shift data into JTDI on
the rising edge and out of JTDO on the falling edge.
JTDO
E5
—
Oz
JTAG Data Out:
Test instructions and data are clocked
out of this pin on the falling edge of JTCLK. If not used,
this pin should be left unconnected.
JTDI
E4
—
Ipu
JTAG Data In:
Test instructions and data are clocked into
this pin on the rising edge of JTCLK. This pin has a 10k
pullup resistor.
JTAG Mode Select:
This pin is sampled on the rising
edge of JTCLK and is used to place the test access port
into the various defined IEEE 1149.1 states. This pin has a
10k pullup resistor.
POWER SUPPLIES
JTMS
F7
—
Ipu
V
DD3.3
G5–G10,
H5–H10
D2, D3,
D12, E3,
E11, E12,
F4, F10,
J4, K4, L3,
L12, M13
A12, D1,
E7, E8,
F8, F9,
F12, F13,
J5–J11,
K3, K5,
K7, K8,
K9, K10,
K12
A7, D4–
D8, H10
I
Connect to 3.3V Power Supply
V
DD1.8
A1, F6,
F10, H2,
J10
I
Connect to 1.8V Power Supply
V
SS
A5, B4,
E4–E7
I
Connect to the Common Supply Ground
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